• 제목/요약/키워드: electrical interfaces compatibility

검색결과 9건 처리시간 0.034초

ELECTRICAL INTERFACES COMPATIBILITY ANALYSIS FOR THE COMS AOCS

  • Koo, Jae-Chun;Kim, Eui-Chan
    • 대한원격탐사학회:학술대회논문집
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    • 대한원격탐사학회 2007년도 Proceedings of ISRS 2007
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    • pp.183-186
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    • 2007
  • The aim of this analysis is to verify the electrical compatibility of the interfaces which exist between COMS(Communication, Ocean and Meteorological Satellite) AOCS(Attitude Orbit Control Subsystem) equipments and external equipments. For each interface, this study checked the compatibility between equipments for the power links, commands, digital telemetry, analog telemetry and failure condition. In addition with this interface compatibility verification, this study outputs the electrical and manufacturing constraints to be applied at harness level.

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통신해양기상위성 진행파관증폭기 전기접속 적합성 해석 (Electrical Interfaces Compatibility Analysis for the COMS TWTA)

  • 구자춘;최재동
    • 항공우주기술
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    • 제7권1호
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    • pp.108-114
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    • 2008
  • 본 해석의 목적은 통신해양기상위성 통신 탑재체의 진행파관증폭기와 외부 유닛들 사이의 전기접속에 대해 적합성을 검증하는 것이다. 본 연구에서는 전력링크, 명령, 디지털 측정, 아날로그 측정 및 실패상태 또는 조립시험 오류들에 대해 유닛들 사이의 적합성을 확인하였다. 본 접속 적합성 검증에 추가적으로 본 연구는 하니스 레벨에서 적용되는 전기 및 제작에서 권고사항을 제공한다.

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통신해양기상위성 휠 전기접속 적합성 해석 (Electrical Interfaces Compatibility Analysis for the COMS Wheels)

  • 구자춘;김의찬
    • 항공우주기술
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    • 제6권1호
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    • pp.103-108
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    • 2007
  • Eurostar 3000 자세제어 시스템은 자세 안정도에 대한 강력한 요구사항 없이 통신 임무에 최적화 되어 있음으로 통신해양기상위성 광학 관찰 임무에서 정밀 자세 안정도 요구사항을 만족하기 위해서는 개선되어야 한다. 이 통신해양기상위성 구성의 제한 사항은 휠에 대해 특수성을 유발시킨다. 본 해석의 목적은 통신해양기상위성 휠과 외부 유닛들 사이의 전기접속에 대해 적합성을 검증하는 것이다. 본 연구에서는 전력링크, 명령, 디지털 측정, 아날로그 측정 및 실패 상태 또는 조립시험 오류들에 대해 유닛들 사이의 적합성을 확인하였다. 본 접속 적합성 검증에 추가적으로 본 연구는 하니스 레벨에서 적용되는 전기 및 제작에서 권고사항을 제공한다.

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New Generation of Lead Free Paste Development

  • Albrecht Hans Juergen;Trodler K. G.
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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    • pp.233-241
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    • 2004
  • A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

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New Generation of Lead Free Solder Spheres 'Landal - Seal'

  • Walter H.;Trodler K. G.
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2004년도 ISMP Pb-free solders and the PCB technologies related to Pb-free solders
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    • pp.211-219
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    • 2004
  • A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

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AMBA AHB와 AXI간 연동을 위한 Switch Wrapper의 설계 (A Switch Wrapper Design for an AMBA AXI On-Chip-Network)

  • 이정수;장지호;이호영;김준성
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2005년도 추계종합학술대회
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    • pp.869-872
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    • 2005
  • In this paper we present a switch wrapper for an AMBA AXI, which is an efficient on-chip-network interface compared to bus-based interfaces in a multiprocessor SoC. The AXI uses an idea of NoC to provide the increasing demands on communication bandwidth within a single chip. A switch wrapper for AXI is located between a interconnection network and two IPs connecting them together. It carries out a mode of routing to interconnection network and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, AHB-AXI converters, interface modules and a controller modules. We propose the design of a all-in-one type switch wrapper.

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Reliable Ethernet Architecture with Redundancy Scheme for Railway Signaling Systems

  • Hwang, Jong-Gyu;Jo, Hyun-Jeong
    • Journal of Electrical Engineering and Technology
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    • 제2권3호
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    • pp.379-385
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    • 2007
  • Recently, vital devices of the railway signaling systems have been computerized in order to ensure safe train operation. Due to this computerization, we have gradually come to need networking interfaces between these devices. Thus it is important that there be reliable communication links in the signaling systems. Network technologies are applied in the real-time industrial control system, and there are numerous studies to be carried out on the computer network technology for vital control systems such as railway signaling systems. For deploying the studies, we consider costs, reliability, safety assurance technique, compatibility, and etc. In this paper, we propose the Ethernet for railway signaling systems and also precisely describe the computer network characteristics of vital railway signaling systems. Then we demonstrate the experimental results of the proposed network algorithm, which is based on switched Ethernet technology with redundancy scheme.

통신해양기상위성 통신탑재체 데이터 접속 적합성 분석 (Data Bus Compatibility Analysis of COMS Communication Payload)

  • 최재동;조영호;김의찬
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2009년도 제40회 하계학술대회
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    • pp.1013_1014
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    • 2009
  • In this paper, the electrical interfaces used in between COMS satellite bus and Ka-band communication payload are analyzed to verify the robustness of data bus. The purpose of the serial data bus of satellite is to allow serial data transfer between one bus controller or source equipment to several user terminals or slave equipments. A serial data bus in COMS satellite is mainly used for Channel Amplifier and Digital Control Unit of Ka-band Payload.

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주차 보조 시스템을 위한 ECU 설계 (Design of Electronic Control Unit for Parking Assist System)

  • 최진혁;이성수
    • 전기전자학회논문지
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    • 제24권4호
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    • pp.1172-1175
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    • 2020
  • 차량에 사용되는 ECU에는 CPU 코어, 차량통신 콘트롤러, 메모리 인터페이스, 센서 인터페이스, I/O 인터페이스 등이 집적되어 있다. 현재 사용되는 차량용 ECU는 대부분 자사만의 독점적 프로세서 아키텍쳐로 개발하였으나, 최근 자율주행자동차 및 커넥티드카에서 소프트웨어 범용성을 위해 ARM, RISC-V와 같은 표준 프로세서를 기반으로 한 차량용 ECU의 수요가 급증하고 있다. 본 논문에서는 명령어 집합이 무료로 공개된 RISC-V를 기반으로 하여 주차 보조 시스템에 사용하기 위한 차량용 ECU를 설계하였다. 개발된 ECU는 32b RISC-V CPU 코어, CAN, LIN 등의 IVN 콘트롤러, ROM, SRAM 등의 메모리 인터페이스, SPI, UART, I2C 등의 I/O 인터페이스를 내장하였다. 65nm CMOS 공정에서 구현한 결과는 동작 주파수 50MHz, 면적 0.37㎟, 게이트 수 55,310개였다.