• Title/Summary/Keyword: electrical interfaces compatibility

Search Result 9, Processing Time 0.032 seconds

ELECTRICAL INTERFACES COMPATIBILITY ANALYSIS FOR THE COMS AOCS

  • Koo, Jae-Chun;Kim, Eui-Chan
    • Proceedings of the KSRS Conference
    • /
    • 2007.10a
    • /
    • pp.183-186
    • /
    • 2007
  • The aim of this analysis is to verify the electrical compatibility of the interfaces which exist between COMS(Communication, Ocean and Meteorological Satellite) AOCS(Attitude Orbit Control Subsystem) equipments and external equipments. For each interface, this study checked the compatibility between equipments for the power links, commands, digital telemetry, analog telemetry and failure condition. In addition with this interface compatibility verification, this study outputs the electrical and manufacturing constraints to be applied at harness level.

  • PDF

Electrical Interfaces Compatibility Analysis for the COMS TWTA (통신해양기상위성 진행파관증폭기 전기접속 적합성 해석)

  • Koo, Ja-Chun;Choi, Jae-Dong
    • Aerospace Engineering and Technology
    • /
    • v.7 no.1
    • /
    • pp.108-114
    • /
    • 2008
  • The aim of this analysis is to verify the electrical compatibility of the interfaces which exist between TWTA(Travelling Wave Tube Amplifier) which is equipment of the Ka-band payload in COMS (Communication, Ocean and Meteorological Satellite) and external equipments. For each interface, this study checked the compatibility between equipments for the power links, commands, digital telemetry, analog telemetry, and failure condition or AIT(Assembly, Integration and Test) errors. In addition with this interface compatibility verification, this study outputs electrical and manufacturing recommendations to be applied at harness level.

  • PDF

Electrical Interfaces Compatibility Analysis for the COMS Wheels (통신해양기상위성 휠 전기접속 적합성 해석)

  • Koo, Ja-Chun;Kim, Eui-Chan
    • Aerospace Engineering and Technology
    • /
    • v.6 no.1
    • /
    • pp.103-108
    • /
    • 2007
  • Eurostar 3000 AOCS is optimized for telecommunication mission with no strong requirement on attitude stability and has therefore to be upgraded to comply with COMS high stability requirements for the optical observations. This COMS configuration constraint induces specificities for the wheel. The aim of this analysis is to verify the electrical compatibility of the interfaces which exist between COMS wheels and external equipments. For each interface, this study checked the compatibility between equipments for the power links, commands, digital telemetry, analog telemetry, and failure condition or AIT errors. In addition with this interface compatibility verification, this study outputs electrical and manufacturing recommendations to be applied at harness level.

  • PDF

New Generation of Lead Free Paste Development

  • Albrecht Hans Juergen;Trodler K. G.
    • Proceedings of the International Microelectronics And Packaging Society Conference
    • /
    • 2004.09a
    • /
    • pp.233-241
    • /
    • 2004
  • A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

  • PDF

New Generation of Lead Free Solder Spheres 'Landal - Seal'

  • Walter H.;Trodler K. G.
    • Proceedings of the International Microelectronics And Packaging Society Conference
    • /
    • 2004.09a
    • /
    • pp.211-219
    • /
    • 2004
  • A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

  • PDF

A Switch Wrapper Design for an AMBA AXI On-Chip-Network (AMBA AHB와 AXI간 연동을 위한 Switch Wrapper의 설계)

  • Yi, Jong-Su;Chang, Ji-Ho;Lee, Ho-Young;Kim, Jun-Seong
    • Proceedings of the IEEK Conference
    • /
    • 2005.11a
    • /
    • pp.869-872
    • /
    • 2005
  • In this paper we present a switch wrapper for an AMBA AXI, which is an efficient on-chip-network interface compared to bus-based interfaces in a multiprocessor SoC. The AXI uses an idea of NoC to provide the increasing demands on communication bandwidth within a single chip. A switch wrapper for AXI is located between a interconnection network and two IPs connecting them together. It carries out a mode of routing to interconnection network and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, AHB-AXI converters, interface modules and a controller modules. We propose the design of a all-in-one type switch wrapper.

  • PDF

Reliable Ethernet Architecture with Redundancy Scheme for Railway Signaling Systems

  • Hwang, Jong-Gyu;Jo, Hyun-Jeong
    • Journal of Electrical Engineering and Technology
    • /
    • v.2 no.3
    • /
    • pp.379-385
    • /
    • 2007
  • Recently, vital devices of the railway signaling systems have been computerized in order to ensure safe train operation. Due to this computerization, we have gradually come to need networking interfaces between these devices. Thus it is important that there be reliable communication links in the signaling systems. Network technologies are applied in the real-time industrial control system, and there are numerous studies to be carried out on the computer network technology for vital control systems such as railway signaling systems. For deploying the studies, we consider costs, reliability, safety assurance technique, compatibility, and etc. In this paper, we propose the Ethernet for railway signaling systems and also precisely describe the computer network characteristics of vital railway signaling systems. Then we demonstrate the experimental results of the proposed network algorithm, which is based on switched Ethernet technology with redundancy scheme.

Data Bus Compatibility Analysis of COMS Communication Payload (통신해양기상위성 통신탑재체 데이터 접속 적합성 분석)

  • Choi, Jae-Dong;Cho, Young-Ho;Kim, Eui-Chan
    • Proceedings of the KIEE Conference
    • /
    • 2009.07a
    • /
    • pp.1013_1014
    • /
    • 2009
  • In this paper, the electrical interfaces used in between COMS satellite bus and Ka-band communication payload are analyzed to verify the robustness of data bus. The purpose of the serial data bus of satellite is to allow serial data transfer between one bus controller or source equipment to several user terminals or slave equipments. A serial data bus in COMS satellite is mainly used for Channel Amplifier and Digital Control Unit of Ka-band Payload.

  • PDF

Design of Electronic Control Unit for Parking Assist System (주차 보조 시스템을 위한 ECU 설계)

  • Choi, Jin-Hyuk;Lee, Seongsoo
    • Journal of IKEEE
    • /
    • v.24 no.4
    • /
    • pp.1172-1175
    • /
    • 2020
  • Automotive ECU integrates CPU core, IVN controller, memory interface, sensor interface, I/O interface, and so on. Current automotive ECUs are often developed with proprietary processor architectures. However, demends for standard processors such as ARM and RISC-V increase rapidly for saftware compatibility in autonomous vehicles and connected cars. In this paper, an automotive ECU is designed for parking assist system based on RISC-V with open instruction set architecture. It includes 32b RISC-V CPU core, IVN controllers such as CAN and LIN, memory interfaces such as ROM and SRAM, and I/O interfaces such as SPI, UART, and I2C. Fabricated in 65nm CMOS technology, its operating frequency, area, and gate count are 50MHz, 0.37㎟, and 55,310 gates, respectively.