• Journal of Navigation and Port Research
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• v.29 no.10 s.106
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• pp.921-926
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• 2005

The purpose of this paper is to conduct a comparative analysis of container terminal operation in Busan and Kwangyang port. The research method used for this study is DEA(Data Envelopment Analysis} and among DEA methods CCR and BCC model has been used. According to the results of CCR model Gamman in 2004 and Gamcheon in 2004 are found to be the most efficient terminals in the sample and the inefficient terminals include Gwangyang Phase 2 terminal. Based on BCC model Gamcheon and Uam are identified as the most efficient terminals in three consecutive years including Gamman terminal in 2004. The inefficient terminals include New Gamman in 2002 and Hutchison in 2002. The research findings show that inefficient terminals need to fully utilise their terminal facilities and increase container throughput through effective marketing activities.

• The Journal of the Korea Contents Association
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• v.17 no.3
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• pp.370-381
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• 2017

Recently, a complex event processing system has been introduced to quickly and efficiently process real-time events in various applications. Since the existing complex event processing schemes do not consider the similarity and duplication of operators, they perform a lot of computations and consume memory. To solve such problems, this paper proposes an efficient complex event processing scheme considering similar operators and duplication operations. When the same primitive events have similar operations, the proposed scheme combines them into one virtual operator. For duplicated operations, the proposed scheme processes only one of them first, and then processes the others using the results of the already processed operation when the same operation is subsequently performed. It is shown through performance comparison that the proposed scheme outperforms the existing scheme in terms of the whole operation throughput.

• Journal of Korea Port Economic Association
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• v.26 no.1
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• pp.1-19
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• 2010

This paper focuses measuring the efficiency of container yards on container terminals in Busan (Gasungdae, Shinsundae, Gamman, New Gamman, Uam, Gamchon, PNC) and Gwangyang(GICT, KEC, Dongbu, KIT) using Data Envelopment Analysis(DEA) approach. Container terminals in Busan and Gwangyang play an important role in the region's economic development. The results show that Shinsundae was an efficient DMU during the period of 2007 to 2009, while Gamman, New Gamman and PNC were efficient terminals in 2009. The very inefficient terminals were shown to be GICT, KEC, Dongbu and KIT. GICT(2009), KEC(2009), Dongbu(2008-2009), KIT(2009) on Gwangyang Port were found to be relatively the inefficient terminals in terms of the returns to scale. This study also finds that the efficiency of Shinsundae terminal was so high as to be abel to keep its efficiency in spite of the additional increase of the inputs from 2007 to 2009. Gamman terminal was in the decreasing returns to scale in 2009, while the other terminals were in the increasing returns to scale. It means that we are able to improve the efficiency of the Gamman terminal with increasing returns to scale through enlarging the scale.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1495-1507
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• 1997

Among a number of approaches to text compression, adaptive dictionary schemes based on a sliding window have been very frequently used due to their high performance. The LZ77 algorithm is the most efficient algorithm which implements such adaptive schemes for the practical use of text compression. This paperpresents a VLSI architecture designed for processing the LZ77 algorithm in parallel. Compared with the other VLSI architectures developed so far, the proposed architecture provides the more viable solution to high performance with regard to its throughput, efficient implementation of the VLSI systolic arrays, and hardware scalability. Indeed, without being affected by the size of the sliding window, our system has the complexity of O(N) for both the compression and decompression and also requires small wafer area, where N is the size of the input text.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2A
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• pp.144-153
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• 2006

In this paper, we propose an efficient video data transmission protocol using the cross-layer approach in ad hoc networks. Due to node movement, the MANET is frequently changing path and each path has different transmission rate so that it has low performance when transmitters select a constant transmission late at the encoding time. Because MANET is running limited energy, efficient energy management is important because it increases network life time and network throughput. Therefore we need an effective video transmission method that considers physical layer channelstatistics, node's energy status, and network topology changes at the same time unlike the OSI recommendation protocol in that each layer isindependent and hard to transmit adaptively video data according to the network conditions. Therefore, in this paper we propose a cross-layer effective video transmission protocol and mechanism that can select an optimal path using multilayer information such as node's residual energy, channel condition and hop counts and can determine the adequate coding rate adaptively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.5A
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• pp.536-542
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• 2011

For efficient utilization of spectrum resources in TV white space after DTV transition, FCC allowed usage of the spectrum for CR system. The CR system is required to cognize channel usage state for utilizing the unused spectrum in TV white space which coexists various primary and secondary systems. In the meantime, as a demand for high throughput communication had been increased recently, CR systems also consider to adopt channel bonding technology, thus spectrum sensing for channel bonded system is essentially required. In this paper, we propose a novel spectrum sensing algorithm for channel bonding system using a single channel receiver. For IEEE 802.l1af signal, the proposed algorithm provide detection probability of 90% with false alarm probability 10% at SNR -18dB for single channel system and at SNR -7dB for 8 channel bonded system, respectively. Utilizing the proposed scheme, we can detect channel bonded signal using only a single receiver, therefore system overhead for spectrum sensing can be reduced significantly.

• Journal of Information Processing Systems
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• v.7 no.2
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• pp.241-260
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• 2011

In earlier days, most of the data carried on communication networks was textual data requiring limited bandwidth. With the rise of multimedia and network technologies, the bandwidth requirements of data have increased considerably. If a network link at any time is not able to meet the minimum bandwidth requirement of data, data transmission at that path becomes difficult, which leads to network congestion. This causes delay in data transmission and might also lead to packet drops in the network. The retransmission of these lost packets would aggravate the situation and jam the network. In this paper, we aim at providing a solution to the problem of network congestion in mobile ad hoc networks [1, 2] by designing a protocol that performs routing intelligently and minimizes the delay in data transmission. Our Objective is to move the traffic away from the shortest path obtained by a suitable shortest path calculation algorithm to a less congested path so as to minimize the number of packet drops during data transmission and to avoid unnecessary delay. For this we have proposed a protocol named as Congestion Aware Selection Of Path With Efficient Routing (CASPER). Here, a router runs the shortest path algorithm after pruning those links that violate a given set of constraints. The proposed protocol has been compared with two link state protocols namely, OSPF [3, 4] and OLSR [5, 6, 7, 8].The results achieved show that our protocol performs better in terms of network throughput and transmission delay in case of bulky data transmission.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.125-128
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• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.2
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• pp.97-102
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• 2010

In this paper, an area-efficient FFT processor is proposed for IEEE 802.16e mobile WiMax systems. The proposed scalable FFT processor can support the variable length of 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 16% and 27%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.