• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.6
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• pp.299-305
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• 2020

We have developed a scheduler that additionally consider network performance by extending the Kubernetes developed to manage lots of containers in cloud computing nodes. The network delay adapt characteristics of the compute nodes were learned during server operation and the learned results were utilized to develop placement algorithm by considering the existing measurement units, CPU, memory, and volume together, and it was confirmed that the low delay network service was provided through placement algorithm.

• Korean Journal of Remote Sensing
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• v.22 no.6
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• pp.601-612
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• 2006

This study proposes RAG (Region Adjancency Graph)-based image segmentation for large imagery in remote sensing. The proposed algorithm uses CN-chain linking for computational efficiency and multi-window operation of sliding structure for memory efficiency. Region-merging due to RAG is a process to find an edge of the best merge and update the graph according to the merge. The CN-chain linking constructs a chain of the closest neighbors and finds the edge for merging two adjacent regions. It makes the computation time increase as much as an exact multiple in the increasement of image size. An RNV (Regional Neighbor Vector) is used to update the RAG according to the change in image configuration due to merging at each step. The analysis of large images requires an enormous amount of computational memory. The proposed sliding multi-window operation with horizontal structure considerably the memory capacity required for the analysis and then make it possible to apply the RAG-based segmentation for very large images. In this study, the proposed algorithm has been extensively evaluated using simulated images and the results have shown its potentiality for the application of remotely-sensed imagery.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• International Journal of Internet, Broadcasting and Communication
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• v.13 no.3
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• pp.104-108
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• 2021

In order to improve performance in IoT, edge computing system, a memory is usually configured in a hierarchical structure. Based on the distance from CPU, the access speed slows down in the order of registers, cache memory, main memory, and storage. Similar to the change in performance, energy consumption also increases as the distance from the CPU increases. Therefore, it is important to develop a technique that places frequently used data to the upper memory as much as possible to improve performance and energy consumption. However, the technique should solve the problem of cache performance degradation caused by lack of spatial locality that occurs when the data access stride is large. This study proposes a technique to selectively place data with large data access stride to a software-controlled cache. By using the proposed technique, data spatial locality can be improved by reducing the data access interval, and consequently, the cache performance can be improved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.662-672
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• 2011

This paper presents a new edge-preserving algorithm and its VLSI architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-preserving maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is prototyped on FPGA Cyclone II, and then we estimated performance when the filter is synthesized on ANAM 0.25 ${\mu}m$ CMOS cell library using Synopsys Design Compiler. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details.

• Journal of the Korea Society of Computer and Information
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• v.16 no.7
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• pp.149-156
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• 2011

This paper proposes the effective edge selection algorithm for the rapid processing time and low memory usage of efficient graph-based image segmentation on mobile device. The graph-based image segmentation algorithm is to extract objects from a single image. The objects are consisting of graph edges, which are created by information of each image's pixel. The edge of graph is created by the difference of color intensity between the pixel and neighborhood pixels. The object regions are found by connecting the edges, based on color intensity and threshold value. Therefore, the number of edges decides on the processing time and amount of memory usage of graph-based image segmentation. Comparing to personal computer, the mobile device has many limitations such as processor speed and amount of memory. Additionally, the response time of application is an issue of mobile device programming. The image processing on mobile device should offer the reasonable response time, so that, the image segmentation processing on mobile should provide with the rapid processing time and low memory usage. In this paper, we demonstrate the performance of the effective edge selection algorithm, which effectively controls the edges of graph for the rapid processing time and low memory usage of graph-based image segmentation on mobile device.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1753-1755
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• 1996

This paper presents an analysis of the 3D microwave oven considering its forming. The results were compared with experimental data. Finite Element Method(FEM) using edge clement is employed for the analysis. For solving the large sparse system matrix equation was solved using the parallelized QMR method. Analysis of the 3d cavity has troublesome difficulties such as spurious solutions, too many memory and long computation time. We overcome this difficulties by using edge clement for spurious solutions and the parallelized QMR method by the aid of Paralle Virtual Machine(PVM) for the memory and computation time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1171-1177
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• 2002

In this paper, we proposed a high speed IP(Internet Protocol) packet forwarding engine of ATM(Asynchronous Transfer Mode) based label edge routers for POS(Packet over SONET) interface. The forwarding engine uses TCAM(Ternary Content Addressable Memory) for high performance lookup processing of the packet received from POS interface. We have accomplished high speed IP packet forwarding in hardware by implementing the functions of high speed IP header Processing and lookup control into FPGA(Field Programmable Gate Array). The proposed forwarding engine has the functions of label edge routers as the lookup controller supports MPLS(Multiprotocol Label Switching) packet processing functionality.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.29-34
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• 2005

This paper describes a novel internal clock generator, called duty cycle-corrected analog synchronous mirror delay (DCC-ASMD). The proposed circuit is well suited for dual edge-triggered systems such as double data-rate synchronous DRAM since it can achieve clock synchronization within two clock cycles with accurate duty cycle correction. To evaluate the performance of the proposed circuit, DCC-ASMD was designed using a $0.35\mu$m CMOS process technology. Simulation results show that the proposed circuit generates an internal clock having $50\%$ duty ratio within two clock cycles from the external clock having duty ratio range of $40\;\~\;60$.

• Korean Journal of Computational Design and Engineering
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• v.14 no.4
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• pp.217-224
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• 2009

Most divide-and-conquer implementations for Delaunay triangulation utilize quad-edge or winged-edge data structure since triangles are frequently deleted and created during the merge process. How-ever, the proposed divide-and-conquer algorithm utilizes the array based data structure that is much simpler than the quad-edge data structure and requires less memory allocation. The proposed algorithm has two important features. Firstly, the information of space partitioning is represented as a permutation vector sequence in a vertices array, thus no additional data is required for the space partitioning. The permutation vector represents adaptively divided regions in two dimensions. The two-dimensional partitioning of the space is more efficient than one-dimensional partitioning in the merge process. Secondly, there is no deletion of edge in merge process and thus no bookkeeping of complex intermediate state for topology change is necessary. The algorithm is described in a compact manner with the proposed data structures and operators so that it can be easily implemented with computational efficiency.