• Journal of KIISE:Computing Practices and Letters
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• v.16 no.11
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• pp.1081-1085
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• 2010

In the wireless sensor networks, power consumption and interference among the nodes can be reduced by using the transmission power control. Because link quality is changed by spatial and temporal effect, link failures are frequently occurred. In order to adapt to link quality variation, existing transmission power control schemes broadcast beacon messages periodically to neighbor nodes and control the transmission power dynamically. However, it can effect on the time and energy overhead according to period of transmission power control. In this paper, the dynamic method of transmission power control by the link quality variation and variable period are proposed. When a link quality is unstable, the control duty cycle is reduced and the link quality is agilely maintained. In contrast, when link quality is stable, the control period is increased and control overhead is decreased.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.1
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• pp.171-184
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• 2010

In this work, we develop a novel channel power allocation method for the real-time multimedia over the wireless network environment. Since each frame has different effect on the user perceivable QoS, improving packet loss does not necessarily coincide with perceivable improvements in QoS. A new channel power control scheme is suggested based on the quantified importance of each frame in terms of user perceivable QoS. Dynamic programming formulation is used to obtain optimal transmit power which minimizes power consumption and maximizes user perceivable QoS simultaneously. The experiment is performed by using publicly available video clips. The performance is evaluated using network simulator version 2 (NS 2) and decoding engine is embedded at the client node, and calculated PSNR over the every frame transmitted. Through the semantics aware power allocation (SAPA) scheme, significant improvement on the QoS has been verified, which is the result of unequal protection to more important packets. SAPA scheme reduced the loss of I frame by upto 27% and reduced power consumption by upto 19% without degradation on the user perceivable QoS.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.62-73
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• 2012

IEEE 802.15.4 standard which has low-speed, low-power, low-cost can be efficiently used in wireless sensor network environment. Among various topologies used in IEEE 802.15.4 standard, a cluster-tree topology which has many nodes in it, transmit delay, energy consumption and data loss due to traffic concentration around the sink node. In this paper, we propose the MRS-DCA algorithm that minimizes conflicts between packets for efficient data transmission, and dynamically allocates the active period for efficient use of limited energy. The MRS-DCA algorithm allocates RP(Reservation Period) to the active period of IEEE 802.15.4 and guarantees reliable data transmission by allocating RP and CAP dynamically which is based on prediction using EWMA. The comparison result shows that the MRS-DCA algorithm reduces power consumption by reducing active period, and increasing transmission rate by avoiding collision.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.1-8
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• 2013

TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy $^*$ Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.417-422
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• 2021

In this paper, a ZQ calibration using a time domain comparator is proposed. The proposed comparator is designed based on VCO, and an additional clock generator is used to reduce power consumption. By using the proposed comparator, the reference voltage and the PAD voltage were compared with a low 1 LSB voltage, so that the additional offset cancelation process could be omitted. The proposed time domain comparator-based ZQ calibration circuit was designed with a 65nm CMOS process with 1.05V and 0.5V supply voltages. The proposed clock generator reduces power consumption by 37% compared to a single time domain comparator, and the proposed ZQ calibration increases the mask margin by up to 67.4%.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2008.11a
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• pp.203-204
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• 2008

Bacterial Cellulose Actuator with biocompatible and biodegradable properties was newly developed as an electro-active biopolymer under water. The performance of the BC actuator was improved through Li treatment. The mechanical and chemical properties of BC membranes were measured such as the tensile test, proton conductivity. The surface morphology of the bacterial cellulose was observed by using SEM. The electromechanical bending responses under both direct current and alternating current excitations were investigated. In voltage-current test,the power consumption under dynamic excitation increases with increasing voltage. Present results show that the bacterial cellulose actuator can be a promising smart material and may possibly have diverse applications under water.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.2
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• pp.142-147
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• 2008

In wireless sensor networks, one of the most important issue is improvement of network lifetime with an efficient energy consumption. we repose effective multi-hop routing algorithm which increases the number of nodes alive at any time. In our algorithm we use the dynamic selection of cluster head and short distance transmission method. We simulated the proposed algorithm by using Network Simulator 2 and compared its performance with LEACH. The experimental result shows that the number of the nodes alive is increased up to 39.71[%] during the simulation time.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1459-1464
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• 1996

The most important parameter for hydraulic active suspension system is to sustain desirable vehicle maneuvering stability and ride comfort without increasing consumption power. The performance of hydraulic active suspension system depends on damping force of body damping valve and piston damping valve. Hydraulic actuator design and damping valve parameter selection are essential and basic procedure to design hydraulic active suspension system. This paper is on computer simulation with use of mathematical model that was delivered from dynamic characteristic of hydraulic actuator, as know basic damping characteristics of hydraulic active suspension system. The aim of this paper is to select the system parameter that affect mainly hydraulic active suspension, and identify the validity on the system parameter selection.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.38-45
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• 2007

A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.