• Title/Summary/Keyword: dynamic operation margin

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Structure & Installation Engineering for Offshore Jack-up Rigs

  • Park, Joo-Shin;Ha, Yeong-Su;Jang, Ki-Bok;Radha, Radha
    • Bulletin of the Society of Naval Architects of Korea
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    • v.54 no.4
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    • pp.39-46
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    • 2017
  • Jack-up drilling rigs are widely used in offshore oil and gas exploration industry. It is originally designed for use in the shallow waters less than 60m of water depth; there is growing demand for their use in deeper water depth over 150m and harsher environmental conditions. In this study, global in-place analysis of jack-up rig leg for North-sea oil well is performed through numerical analysis. Firstly, environmental conditions and seabed characteristics at the North-sea are collected and investigated measurements from survey report. Based on these data, design specifications are established and the overall basic design is performed. Dynamic characteristics of the jack-up rig for North-sea are considered in the global in-place analysis both leg and hull and the basic stability against overturning moment is also analyzed. The structural integrity of the jack-up rig leg/hull is verified through the code checks and the adequate safety margin is observed. The uncertainty in jack-up behaviour is greatly influenced by the uncertainties in the soil characteristics that determine the resistance of the foundation to the forces imposed by the jack-up structure. Among the risks above mentioned, the punch-through during pre-loading is the most frequently encountered foundation problem for jack-up rigs. The objective of this paper is to clarify the detailed structure and installation engineering matters for prove the structural safety of jack-up rigs during operation. With this intention the following items are addressed; - Characteristics of structural behavior considering soil effect against environmental loads - Modes of failure and related pre-loading procedure and parameters - Typical results of structural engineering and verification by actual measurement.

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INNOVATIVE CONCEPT FOR AN ULTRA-SMALL NUCLEAR THERMAL ROCKET UTILIZING A NEW MODERATED REACTOR

  • NAM, SEUNG HYUN;VENNERI, PAOLO;KIM, YONGHEE;LEE, JEONG IK;CHANG, SOON HEUNG;JEONG, YONG HOON
    • Nuclear Engineering and Technology
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    • v.47 no.6
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    • pp.678-699
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    • 2015
  • Although the harsh space environment imposes many severe challenges to space pioneers, space exploration is a realistic and profitable goal for long-term humanity survival. One of the viable and promising options to overcome the harsh environment of space is nuclear propulsion. Particularly, the Nuclear Thermal Rocket (NTR) is a leading candidate for nearterm human missions to Mars and beyond due to its relatively high thrust and efficiency. Traditional NTR designs use typically high power reactors with fast or epithermal neutron spectrums to simplify core design and to maximize thrust. In parallel there are a series of new NTR designs with lower thrust and higher efficiency, designed to enhance mission versatility and safety through the use of redundant engines (when used in a clustered engine arrangement) for future commercialization. This paper proposes a new NTR design of the second design philosophy, Korea Advanced NUclear Thermal Engine Rocket (KANUTER), for future space applications. The KANUTER consists of an Extremely High Temperature Gas cooled Reactor (EHTGR) utilizing hydrogen propellant, a propulsion system, and an optional electricity generation system to provide propulsion as well as electricity generation. The innovatively small engine has the characteristics of high efficiency, being compact and lightweight, and bimodal capability. The notable characteristics result from the moderated EHTGR design, uniquely utilizing the integrated fuel element with an ultra heat-resistant carbide fuel, an efficient metal hydride moderator, protectively cooling channels and an individual pressure tube in an all-in-one package. The EHTGR can be bimodally operated in a propulsion mode of $100MW_{th}$ and an electricity generation mode of $100MW_{th}$, equipped with a dynamic energy conversion system. To investigate the design features of the new reactor and to estimate referential engine performance, a preliminary design study in terms of neutronics and thermohydraulics was carried out. The result indicates that the innovative design has great potential for high propellant efficiency and thrust-to-weight of engine ratio, compared with the existing NTR designs. However, the build-up of fission products in fuel has a significant impact on the bimodal operation of the moderated reactor such as xenon-induced dead time. This issue can be overcome by building in excess reactivity and control margin for the reactor design.

A 0.31pJ/conv-step 13b 100MS/s 0.13um CMOS ADC for 3G Communication Systems (3G 통신 시스템 응용을 위한 0.31pJ/conv-step의 13비트 100MS/s 0.13um CMOS A/D 변환기)

  • Lee, Dong-Suk;Lee, Myung-Hwan;Kwon, Yi-Gi;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.3
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    • pp.75-85
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    • 2009
  • This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.