• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.5B no.4
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• pp.366-373
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• 2005

This paper presents two new circuit topologies of the dc busline side active resonant snubber assisted voltage source high frequency link soft switching PWM full-bridge dc-dc power converters acceptable for either utility ac 200V-rms or ac 400V-rms input grid. These high frequency switching dc-dc converters proposed in this paper are composed of a typical voltage source-fed full-bridge PWM inverter, high frequency transformer with center tap, high frequency diode rectifier with inductor input filter and dc busline side series switches with the aid of a dc busline parallel capacitive lossless snubber. All the active switches in the full-bridge arms as well as dc busline snubber can achieve ZCS turn-on and ZVS turn-off transition commutation with the aid of a transformer leakage inductive component and consequently the total switching power losses can be effectively reduced. So that, a high switching frequency operation of IGBTs in the voltage source full bridge inverter can be actually designed more than about 20 kHz. It is confirmed that the more the switching frequency of full-bridge soft switching inverter increases, the more soft switching PWM dc-dc converter with a high frequency transformer link has remarkable advantages for its power conversion efficiency and power density implementations as compared with the conventional hard switching PWM inverter type dc-dc power converter. The effectiveness of these new dc-dc power converter topologies can be proved to be more suitable for low voltage and large current dc-dc power supply as arc welding equipment from a practical point of view.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.151-161
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• 2013

An active power factor correction (PFC) circuit is presented which employs a newly proposed input voltage sensor-less control technique operated in continuous conduction mode (CCM) and critical conduction mode (CRM). The conventional PFC circuit with input voltage sensor-less control technique degrades the power factor (PF) under the light load condition due to DCM operation. In the proposed PFC circuit, the switching frequency is basically 70KHz in CCM operation. In light load condition, however, the PFC circuit operates in CRM and the switching frequency is increased up to 200KHz. So CCM/CRM operation of the PFC circuit alleviates the decreasing of the PF in light load condition. The proposed PFC controller IC has been implemented in a $0.35{\mu}m$ BCDMOS process and a 240W PFC prototype is built. Experimental results shows the PF of the proposed PFC circuit is improved up to 10% from the one employing the conventional CCM/DCM dual mode control technique. Also, the PF is improved up to 4% in the light load condition of the IEC 61000-3-2 Class D specifications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.830-838
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• 2003

In this paper, TX/RX dual operation microstrip single antenna for satellite communication is designed, analyzed, fabricated and measured. TX/RX frequency ranges are 14.0∼l4.5 GHz, 11.7∼12.75 GHz in respectively and vertical and horizontal polarizations are used for TX and RX. This antenna uses microstrip direct feeding for RX and aperture coupled strip-line feeding for TX and accommodates stacked elements for a high directivity and wide impedance bandwidth. In an analysis of single element, FDTD and MOM was compared and FDTD analysis was more accurate because of the consideration of finite structure and imperfect two ground planes. The proposed structure facilitates generally to an extension of two dimensional array and lower an unwanted radiation by strip-line feed in TX. TX/RX 8${\times}$4 array has a return loss below -10 dB, -14 dB in TX, RX respectively and a gain ranging from 19.1∼20.7 dB in TX, 21.2∼21.8 dB in RX which has a radiation efficiency of 43∼5l %, 52∼57 %.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.3
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• pp.337-341
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• 2011

This paper presents the design of a novel integrated mobile antenna for vehicles. The proposed antenna fabricated on a low cost easily available FR4 substrate, which effectively covers both dual band operation. The proposed mobile antenna is a modified G-type patch antenna that can operate in various frequency bands, GSM (880~960 MHz), AMPS (824~894MHz), DCS (1710~1880MHz), PCS (1850~1990MHz), UMTS (1920~2170). Experimental results indicate that the impedance bandwidth (VSWR 1:2.5) of the proposed mobile antenna agree that of the simulation results. It was validated that the configuration can meet the demands of Mobile frequency bands and effectively enhanced the impedance bandwidth to 36.46% for the lower band and 27.84% for the upper band. This paper also presents and discusses the 3D radiation patterns and gains according to the results of the experiment.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.68-73
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• 2013

In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.7
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• pp.515-522
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• 2018

An orthogonal frequency division multiplexing with coded direct index modulation(OFDM-CDIM) system that can achieve higher performance and spectral efficiency than previous OFDM systems is proposed. Previous OFDM with index modulation(IM) and OFDM-IM using dual modes systems allocate additional data to indices of respective subcarriers through combining operation with high complexity and then transmit them. However, the proposed system directly allocates the mode selection information to each subcarrier without performing additional operations. Then, the system selects and transmits one symbol in the selected mode. Furthermore, only the data allocated to the index of the subcarrier is encoded, and a good performance improvement effect is obtained with a high code rate. Simulation results show quantitatively that an OFDM-CDIM system using four modes improves bit error rate performance and transmission efficiency in additive white Gaussian noise and Rayleigh fading channel environments compared with a conventional OFDM system using 4-ary quadrature amplitude modulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.8
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• pp.781-787
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• 2004

In this paper, a novel dual and wide band aperture stacked patch antenna for Cellular/PCS/IMT-2000 base station is presented. It consists of single microstrip patch having notches along the radiating patch, two dielectric substrates and a form material. To achieve wide band characteristic, we utilize the coupling effect between the notched patch and the resonant aperture in the ground plane and by properly cutting notches on the patch, an aperture stacked patch antenna could be designed to yield dual frequency operation. By the proper choice of resonant aperture size and height of a foam material, dual and wide band characteristic could be realized the measured impedance bandwidth(1:1.5 VSWR) of designed antenna at lower band(860 MHz) reaches 77 MHz and covers the Cellular CDMA band(824∼894 MHz). The measured impedance bandwidth(1:1.5 VSMR) of the designed antenna at upper band(1,960 MHz) is about 550 MHz and covers both the PCS band(1,750∼l,870 MHz) and the for-2000 band(1,920∼2,170 MHz). Good broadside radiation with high gain(5.65∼7.4 dBi) characteristics have also been observed.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.1
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• pp.91-96
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• 2018

In this paper, dual axes waveguide rotary joint, which operates at high power and has low loss characteristic, is designed and fabricated for a Ka-band millimeter-wave small radar. Its electrical performance is verified through the S-parameter at room temperature, high power and operation temperature test. Rotary joint functionally consists of the mode converter transforming rectangular waveguide into circular waveguide and the choke at the rotation part. At the configuration design, linking a fixed transmitter to an antenna rotating dual axes electrically for minimum loss and light weight body are considered. In Fc(center frequency)${\pm}500MHz$, the designed rotary joint has VSWR 1.5:1 below return loss, -2.0 dB above insertion loss. It is found that rotary joint characteristics is similar to design results.