• Journal of Electrical Engineering and Technology
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• 제11권1호
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• pp.143-149
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• 2016

The two-stage converter is widely used in traditional DC/AC inverter. It has several disadvantages such as complex topology, large volume and high loss. In order to overcome these shortcomings, a novel half load-cycle worked dual SEPIC single-stage inverter, which is based on the analysis of the relationship between input and output voltages of SEPIC converters operating in the discontinuous conduction mode (DCM), is presented in this paper. The traditional single-stage inverter has remarkable advantages in small and medium power applications, but it can’t realize boost DC/AC output directly. Besides one pre-boost DC/DC converter is needed between the DC source and the traditional single-stage inverter. A novel DC/AC inverter without pre-boost DC/DC converter, which is comprised of two SEPIC converters, is studied. The output of dual SEPIC converters is connected with anti-parallel and half load-cycle control is used to realize boost and buck DC/AC output directly and work properly, whatever the DC input voltage is higher or lower than the AC output voltage. The working principle, parameter selection and the control strategy of the inverters are analyzed in this paper. Simulation and experiment results verify the feasibility of the new inverter.

• Journal of Power Electronics
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• 제16권6호
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• pp.2057-2066
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• 2016

An extension of the one-cycle control (OCC) method for switched-capacitor (SC) converters is proposed in this paper, featuring a fast dynamic response, wide line and load operation ranges, and simplicity in implementation. To illustrate the operation principle of this nonlinear control method and to demonstrate its simplicity in design, a dual-phase unity gain SC converter is examined. A new control loop based on the charge balance in a flying capacitor is formulated for the OCC technique and implemented with a 15W dual-phase unity gain SC converter on a circuit board for control verification. The obtained experimental results show that external disturbances can be rejected in one switching cycle by the OCC controlled SC converter with good line and load regulations. When compared to other control methods, the proposed nonlinear control loop exhibits superior dynamic performance in suppressing input and load disturbances.

• 대한조선학회논문집
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• 제49권1호
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• pp.33-44
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• 2012

In this study, the optimal operating conditions for the dual mixed refrigerant(DMR) cycle were determined by considering the power efficiency. The DMR cycle consists of compressors, heat exchangers, seawater coolers, valves, phase separators, tees, and common headers, and the operating conditions include the equipment's flow rate, pressure, temperature, and refrigerant composition per flow. First, a mathematical model of the DMR cycle was formulated in this study by referring to the results of a past study that formulated a mathematical model of the single mixed refrigerant(SMR) cycle, which consists of compressors, heat exchangers, seawater coolers, and valves, and by considering as well the tees, phase separators, and common headers. Finally, in this study, the optimal operating conditions from the formulated mathematical model was obtained using a hybrid optimization method that consists of the genetic algorithm(GA) and sequential quadratic programming(SQP). Moreover, the required power at the obtained conditions was decreased by 1.4% compared with the corresponding value from the past relevant study of Venkatarathnam.

• 대한전자공학회논문지TE
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• 제39권1호
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• pp.16-21
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• 2002

본 논문에서는 TSPC(True Single Phase Clocking) CMOS 회로를 이용하여 출력특성을 향상시킨 고속 PLL을 위한 이중구조 PFD(Phase Frequency Detector)를 제안한다. 넓은 dead zone과 긴 지연시간을 갖고 있는 기존의 3-state PFD는 고속 동작에 사용되는 PLL(Phase-Locked Loop)에서 사용하는 것은 부적합하다. 이러한 3-state PFD의 단점을 해결하기 위하여 다이내믹 CMOS 논리회로로 구현된 다이내믹 PFD는 duty cycle의 변화에 따라 지터 잡음을 발생하는 문제점을 갖는다. 이러한 문제를 해결하기 위하여 TSPC 회로와 이중구조를 갖도록 설계되어 제안된 PFD는 dead zone과 duty cycle의 제한조건을 개선하였고, 지터잡음과 응답특성을 개선하였다. 즉, 이중구조를 갖는 PFD는 상승에지에서 동작하는 P-PFD(Positive edge triggered PFD)와 하강에지에서 동작하는 N-PFD(Negative edge triggered PFD)로 구성하여 이득을 증가시켜 응답특성을 개선한다. 제한된 내용의 입증을 위하여 Hspice 시뮬레이션을 수행하였다. 제안된 PFD는 dead zone이 존재하지 않으며, duty cycle의 변화에도 안정된 결과를 나타내며 응답특성이 우수함을 확인할 수 있었다.

• 대한전자공학회논문지SD
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• 제42권9호
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• pp.29-34
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• 2005

본 논문에서는 duty cycle-corrected analog synchronous mirror delay(DCC-ASMD)라고 불리는 새로운 구조의 내부 클럭 생성기를 제안한다. 제안된 회로는 임의의 duty ratio를 가진 외부 클럭에 대하여 duty ratio가 $50\%$로 보정된 내부 클럭을 2클럭 주기 만에 생성할 수 있다. 그러므로, 본 내부 클럭 생성기는 double data-rate (DDR) synchronous DRAM (SDRAM)과 같은 듀얼 에지 동기형 시스템(dual edge-triggered system)에 효율적으로 이용될 수 있다. 제안된 기술의 타당성을 평가하기 위하여, $0.35\mu$m CMOS 공정기술을 이용하여 제안된 내부 클럭 생성기를 구현하여 모사실험을 실행하였다. 실험 결과, 제안된 내부 클럭 생성기는, $40\~60$의 duty ratio를 갖는 외부 클럭 신호에 대하여, 50$\%$ duty ratio를 갖는 내부 클럭 신호를 2 클럭 주기 만에 발생시킬 수 있음을 확인하였다.

• 연구논문집
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• 통권27호
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• pp.75-86
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• 1997

Combined cycle power plant is a system where a gas turbine or steam turbine is used to produce shaft power to drive a generator for producing electrical power and the steam from the HRSG is expanded in a steam turbine for additional shaft power. Combined cycle plant is a one from of cogeneration. The temperature of the exhaust gases from a gas turbine ranges from $400^\circC$ to $600^\circC$, and can be used effectively in a heat recovery steam generator to produce steam. Combined cycle can be classed as a "topping(gas turbine)" and a "bottoming(steam turbine)" cycle. The first cycle, to which most of the heat is supplied, is called the topping cycle. The wasted heat it produces is then utilized in a second process which operates at a lower temperature level and is therefore referred to as a "bottoming cycle". The combination of gas/steam turbine power plant managed to be accepted widely because, first, each individual system has already proven themselves in power plants with a single cycle, therefore, the development costs are low. Secondly, the air as a working medium is relatively non-problematic and inexpensive and can be used in gas turbines at an elevated temperature level over $1000^\circC$. The steam process uses water, which is likewise inexpensive and widely available, but better suited for the medium and low temperature ranges. It, therefore, is quite reasonable to use the steam process for the bottoming cycle. Only recently gas turbines attained inlet temperature that make it possible to design a highly efficient combined cycle. In the present study, performance analysis of a dual pressure combined-cycle power plant is carried out to investigate the influence of topping cycle to combined cycle performance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.779-782
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• 1998

This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.

• 한국사회복지학
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• 제45권
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• pp.288-314
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• 2001

The purpose of this study is to examine the strategies that may influence the marital satisfaction of dual-earner men and women. General linear model, Pearson's correlation analysis, Stepwise multiple regression were employed for data analysis. the subjects are 396 dual-earner men and women. The result from the research were as follows: 1) coping strategy use differs significantly by life cycle stage. 2) The following strategies significantly correlated with the level of marital satisfaction: cognitive restructuring, delegation. using social support, modifying standards, personal time reducing. 3) The result of stepwise multiple regression analysis indicated that strategies which predict the level of marital satisfaction were cognitive restructuring, delegating, using social support, personal time reducing. these finding give us significant practical implications for social work intervention.

• 대한전자공학회논문지TC
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• 제41권10호
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• pp.79-86
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• 2004

본 논문은 0.35㎛ CMOS 공정을 이용하여 1.070GHz와 2.07GHz의 주파수를 생성해내는 이중 대역 전압 제어 발진기를 제안한다. 50% 듀티 싸이클 회로와 반가산기를 가진 제안된 전압 제어 발진기는 일반적인 전압 제어 발진기의 주파수보다 두 배 높은 주파수를 생성해낼 수 있다 제안된 전압 제어 발진기의 측정 결과는 전압 제어 발진기 이득과 전력 소모가 각각 561MHz/V, 14.6mW로 나타났다. 이중 대역 전압 제어 발진기의 위상 잡음은 각각 1.07GHz와 2.07GHz로부터 2MHz 옵셋 주파수에서 -102.55dBc/Hz와 -95.88dBc/Hz로 측정되었다.

• Journal of Power Electronics
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• 제15권1호
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• pp.268-277
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• 2015

In this paper, a dual-converter three-phase pulse width modulation (PWM) rectifier based on unbalanced one-cycle control (OCC) strategy is proposed. The proposed rectifier is used to eliminate the second harmonic waves of DC voltage and distortion of line currents under unbalanced input grid voltage conditions. The dual-converter PWM rectifier employs two converters, which are called positive-sequence converter and negative-sequence converter. The unbalanced OCC system compensates feedback currents of positive-sequence converter via grid negative-sequence voltages, as well as compensates feedback currents of negative-sequence converter via grid positive-sequence voltages. The AC currents of positive- and negative-sequence converter are controlled to be symmetrical. Thus, the workload of every switching device of converter is balanced. Only one conventional PI controller is adopted to achieve invariant power control. Then, the parameter tuning is simplified, and the extraction for positive- and negative-sequence currents is not needed anymore. The effectiveness and the viability of the control strategy are demonstrated through detailed experimental verification.