• Journal of the Korean Society for Precision Engineering
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• v.19 no.11
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• pp.211-220
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• 2002

Optical disk drives read information by replacing a laser beam on the disk track. As information has become larger, the more accurate position control of a laser beam is necessary. In this paper, we report the analysis and fabrication of the micro mirror for optical disk drivers. A coupled simulation of gas flow and structural displacement of the micro mirror using the Finite-Element-Method is applied to this. The mirror was fabricated by using MEMS technology. Especially, the process using the lapping and polishing step after the bonding of the mirror and electrode plates was employed for the Process reliability. The mirror size was 2.5mm${\times}$3mm and it needed about 35V for displacement of 3.2 ${\mu}$.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.5 no.3
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• pp.299-305
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• 1995

Visible photoluminescing (PL) silicon at room temperature has been prepared by a dry technique, that is, by spark processing, contrary to anodically etched porous silicon. PL peak maximum of photoluminescing spark processed Si was shifted to blue 520 nm. The stability of spark processed Si towards degradation upon UV radiation was found to be extremely high. Results from high resolution TEM, XRD and XPS studies suggest that spark processed silicon involves minute nanocrystalline (polycrystalline) particles which are imbedded in an amorphous matrix, preferably $SiO_2$.

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.304-307
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• 2013

Reverse engineering of semiconductor devices utilizes delayering processes, in order to identify how the interconnection lines are stacked over transistor gates. Cu metal has been used in recent fabrication technologies, and de-processes becomes more difficult with the shrinking device dimensions. In this article, reverse engineering technologies to reveal the Cu interconnection lines and Cu via-plugs embedded in dielectric layers are investigated. Stacked dielectric layers are removed by $CF_4$ plasma etching, then the exposed planar Cu metal lines and via-plugs are selectively delineated by wet chemical solution, instead of the commonly used plasma-based dry etch. As a result, we have been successful in extracting the layouts of multiple layers within a system IC, and this technique can be applicable to other logic IC, analog IC, and CMOS IC, etc.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1497_1498
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• 2009

This paper presents the simulation of micro-lens arrays based on dry and wet etching technique. Code V (Optical Research Associates Ltd) simulation was performed to extract optimal design parameters of a Micro-Lens Array(MLA). Thickness of UV adhesive, wavelength of laser source, curvature, and shape of lens surface were chosen for the design parameters. The simulation results showed that focal length of a MLA decreased with the increase of UV adhesive thickness. And the focal length depended on shape of lens surface and length of laser source.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1515_1516
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• 2009

A 440MHz wireless and passive surface acoustic wave (SAW) based micro-sensor was developed for simultaneous measurement of temperature and humidity. The developed sensor is composed of a SAW reflective delay lines structured by an IDT (Inter-Digital Transducer), four reflectors and humidity sensitive film (polyimide). Polyimide was dry-ecthed by RIE (Reactive Ion Etching) to obtain high roughness, which gives the large reaction area resulting in high sensitivity. In wireless testing using a network analyzer, sharp reflection peaks with high S/N ratio, small signal attenuation, and few spurious peaks were observed in the time domain. High sensitivity towards the temperature and humidiy were also observed in the large concentration range. The obtained sensitivity was $16.8^{\circ}/^{\circ}C$ for temperature sensor and $15.8^{\circ}$/%RH for humidity sensor.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.600-600
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• 2013

We have fabricated Cr nanodot Schottky diodes utilizing AAO templates formed on n-Si substrates. Three different sizes of Cr nanodots (about 75.0, 57.6, and 35.8 nm) were obtained by controlling the height of the AAO template. Cr nanodot Schottky diodes showed a rectifying behavior with low SBHs of 0.17~0.20 eV and high ideality factors of 5.6~9.2 compared to those for the bulk diode. Also, Cr nanodot Schottky diodes with smaller diameters yield higher current densities than those with larger diameters. These electrical behaviors can be explained by both Schottky barrier height (SBH) lowering effects and enhanced tunneling current due to the nanoscale size of the Schottky contact. Also, we have fabricated Cr-Si nanorod Schottky diodes with three different lengths (130, 220, and 330 nm) by dry etching of n-Si substrate. Cr-Si nanorod Schottky diodes with longer nanorods yield higher reverse current than those with shorter nanorods due to the enhanced electric field, which is attributed to a high aspect ratio of Si nanorod.

• Current Photovoltaic Research
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• v.4 no.3
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• pp.119-123
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• 2016

We discussed various cover glass substrates available for photovoltaic (PV) modules, and investigated the fabrication methods of light trapping structures for the efficiency enhancement of PV modules: wet and dry etching or laser and direct patternings. We also introduced the analysis of haze at etched glass surfaces as a function of wavelength and also presented a anti-reflection coating technology for PV module.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.231-236
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• 2005

To investigate the electrical properties at the single grainboundary of ZnO varistors, micro-electrodes were fabricated on the surface which was polished and thermally etched. Our micro-electrode had 2000 $\AA$ silicon nitride layer between micro-electrode and ZnO surface. This layer was deposited by PECVD and etched by RIE after photoresistor pattering process using by mask 1. The metal patterning of micro-electrodes used lift-off method. We found that the breakdown voltage of single grainboundary is about 3.5∼4.2 V at 0.1 mA on I-V curves. Also, capacitance-voltage measurement at single grainboundary gave several parameters( $N_{d}$, $N_{t}$, $\Phi$$_{b}$, t) which were related with grainboundary.ary.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.149-155
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• 1996

A new technique wasdeveloped which obtains selectively the htick fully recessed oxidized porous silicon layer (OPSL) with good dielectric property. The porous silicon layer was ocnverted to thick fully recessed oxide (FRO) with 3-step (1${\mu}$m, 1.5${\mu}$m, 1.8${\mu}$m) by multi-step thermal oxidation (after 400$^{\circ}$C, 1 hour by dry oxidation, 700$^{\circ}$C, 1 hour and then 1100$^{\circ}$C, 1 hour by wet oxidation). The breakdwon field of the FRO was about 2.5MV/cm and the leakage current was several pA ~ 100 pA in the range of 0 of 90 pF. The progress of oxidation of a porous silicon layer was studied by examining the infrared abosrption spectra. The refractive index (1.51) of the fRO, which was measured by ellipsometer, was comparable to that of the thermally grown silicon dioxide (1.46). The etching rate (1600${\AA}$/min) of the FRO was also almost equal to that of the thermal oxide.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.3
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• pp.102-105
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• 2001

A parametric cmpariosn of etch rate and etch selectivity has been performed for GaN, InN and AIN etched in chlorine- and boron halides-based Inductively Coupled Plasma (ICP) discharges. Chlorine-based chemistries produced controllable etch rates (50~150 nm/min) and maximum etch selectivities ~6 for InN over GaN and ~10 for InN over AlN. Maximum etch selectivities of ~100 for InN over GaN and InN over AlN were obtained in boron halides-based discharges and smooth etched surface morphologies were also achieved.