• Journal of IKEEE
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• v.23 no.2
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• pp.407-412
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• 2019

Many industrial regions has used and extended the application of LED driver because of many advantage. Specially, due to the simplicity, miniaturization and power density, the flyback converter is selected by a lot of power engineer. Also, the electrolytic capacitor in this converter is used for the constant DC voltage of the converter because of the sufficient capacitance and the economic price. However, because of the characteristics of the electrolytic capacitor and ripple currents on the converter. the expected lifetime of the LED driver is more and more shorted. In this paper, a single-stage CCM PFC flyback converter with the film capacitor is suggested to extended the lifetime of the LED driver. In addition, the proposed converter with the LC filter is decreased the ripple current of the converter output.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.629-631
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• 2004

The proposed output buffer is presented for driving large-size LCD panels. This output buffer is designed by adding some simple circuitry to the conventional two-stage operational amplifier. The proposed circuit is simulated in a high-voltage 0.35um CMOS process with HSPICE. The simulated result is more improved settling time than that of conventional one.

• Journal of Electrical Engineering and Technology
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• v.10 no.6
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• pp.2334-2342
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• 2015

This paper proposes an LED driving circuit with a digital controller, power factor correct (PFC) function, and low light flicker. The key topology of the proposed circuit is a conventional Flyback combined with a pre-stage. As a result, there will be less light flicker than with other one-stage PFC circuits. A digital controller, implemented using a low-cost microcontroller, dsPIC30F2020, will meet PFC and low light flicker. The experimental results validate the functionality of the proposed circuit.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.34-38
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• 2006

A low cost PDP sustain power supply is proposed based on flyback topology. By using Boundary Conduction Method(BCM) to control input current regulation, DCM condition can be met under all load conditions. Another feature of the proposed method is that a excessive voltage stress due to the link voltage increase can be suppressed by removing link capacitor and suggest new 'Level-shifting switch driver'. this new gate driver is improved 66% of efficiency than switching loss of a existed push-pull amplifier. The proposed converter is tested with a 400W(200V-2A output) prototype circuit.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.502-505
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• 2002

A singl-phase power factor corrected converter for switched reluctance motor driving is presented to achieve sinusoidal, near unity power factor input currents. Because it combines a power factor corrected converter and a conventional asymmetric SRM driver Into one power stage, the configuration has a simple structure resulted in low cost. A prototype to drive 6/6 poles SRM employing a parking magnet is designed to evaluate the proposed topology The characteristics and operational mode will be discussed in depth, and the validity of proposed driver will be verified through the experimental results.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.4
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• pp.76-83
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• 2003

To cope with stringent performance targets requested in many fields spanning the whole range of industry, the driver is necessary to realize large dynamic range as well as nano resolution, manipulate the mover orientation without additional driver, and be suitable for clean environment. As one of those purposes, authors have developed the planar precision stages with the integrated operating principle of levitation and propel. In this paper, we discuss potential of magnetic suspension technology by comparing various features of non-contact planar stages, that is, repulsive type of surface actuator and attractive type of surface actuator.

• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• The Korean Journal of Applied Statistics
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• v.14 no.1
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• pp.103-110
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• 2001

This paper considers a multistage experiment. Response scales can be same or different from stage to stage. When variables are of nested structure, the response variable at each stage can be defined conditionally. For analysing such data with compound scales, this paper suggests a sequnce of dependence models and shows how to set up a sequence of models for the driver's liscense test data.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1011-1014
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• 2003

We proposed a new two-stage operational amplifier that increases the slew rate by adding some simple circuitry to the conventional structure. The proposed circuit is simulated by HSPICE and the slew rate of the proposed circuit is improved more than 10 times than that of conventional one in slewing state without considerable increments in area and power consumption.