• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.270-271
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• 2008

The contact resistance between organic semiconductor and source-drain electrode in Bottom Contact Organic Thin-Film Transistors (BCOTFTs) can be effectively reduced by metal oxide/molybdenum double layer structure; metal oxide layers including nickel oxide (NiOx/Mo) and moly oxide(MoOx) under molybdenum work as a high performance carrier injection layer. Step profiles of source-drain electrode can be easily achieved by simultaneous etching of the double layers using the difference etching rate between metal oxides and metal layers.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.6
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• pp.951-957
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• 1994

We present a new model for the series resistance of inverted-staggered amorphous silicon (a-Si) thin film transistors (TFT's) by employing the current spreading under the source and the drain contacts as well as the space charge limited current model. The calculated results based on our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which have been verified successfully by the experimental measurements.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.05a
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• pp.86-89
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• 1995

In this pacer, The effect of the impedances in SNOSEFT s memory devices has been developed. The effect of source and drain impedances are measuring using the method of the field effect bias resistance in the inner resistance regions of the device structure and external bias resistance. The effect of impedance by source and drain resistance shows according to increasing to the storage of memory charges, shows according to a function of decreasing to the gate voltages, shows the delay of threshold voltages, The delay time of low conductance state and high conductance state by the impedance effect shows 3 [${\mu}$sec] and 1[${\mu}$sec] respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.10
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• pp.885-888
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• 2008

We present simulation results on DC characteristics of AlGaN/GaN HEMTs having trench shaped source/drain Ohmic electrodes. In order to reduce the contact resistance in the source and drain region of the conventional AlGaN/GaN HEMTs and thereby to increase their DC output power, we applied narrow-shaped-trench electrode schemes whose size varies from $0.5{\mu}m$ to $1{\mu}m$ to the standard AlGaN/GaN HEMT structure. As a result, we found that the drain current was increased by 13 % at the same gate bias condition and the transconductance (gm) was improved by 11 % for the proposed AlGaN/GaN HEMT, compared with those of the conventional AlGaN/GaN HEMTs.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.13 no.5
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• pp.356-367
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• 2001

A numerical analysis on branch type sparger in drain tank for depressurization is performed to investigate the flow characteristics due to the change of design factor. As the result of this study, sparger\\`s flow resistance coefficient(K) is 3.53 at the present design condition when engineering margin for surface roughness is considered as 20%, and flow ratio into branch pipe ($Q_s/Q_i$) is 0.41. The correlation for calculating flow resistance coefficients as design factor is presented. Flow resistance coefficient is increased as section area ratio of branch pipe for main pipe and outlet nozzle diameter of main pipe decreasing, but the effects of branch angle and inlet flow rate of main pipe are small. As the change rate of ($Q_s/Q_i$)becomes larger, the change rate of flow resistance coefficient increases. The rate of pressure loss has the largest change as section area ratio changing. The condition of maximum flow resistance in sparger is when the outlet nozzle diameter ratio of main pipe ($D_e/D_i$) is 0.167, the section area ratio ($A_s/A_i$) is 0.1 and the branch angle ($\alpha$) is 55^{\circ}$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.2
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• pp.104-110
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• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

• 기술발표회
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• s.2006
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• pp.261-269
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• 2006

Recently, piezocone penetration test is frequently used in order to estimate the characteristics of soft ground with standard penetration test; generally used in the past In this study, standard penetration test, piezocone penetration test, driving resistance of vertical drain were used in order to increase the confidence for determination of soft ground depth. And the compressible layer was determined by the comparison between the preconsolidation pressure and the designed increase pressure. As the results, the relation between standard penetration test and piezocone penetration test shows $q_c$=(1.09~1.63)N at the soft ground, determined by 5/30 N value. And $q_c$(1.21~1.98)N was shown at the point of compressible layer, evaluated by the preconsolidation pressure. And driving resistance of vertical drain is 70 f/$cm^2$ which is equal to 10kgf/$cm^2$ cone penetration resistance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.1
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• pp.74-80
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• 1990

The transconductance of short channel LDD MOSFETs in the saturation region (high Vd)has shown different characteristics from that of conventional device. The transconductance in saturation regime of short channel LDD MOSFETs is reduced from maximum value at higher gate voltage. This decline is analyzed as the velocity saturation effects of carrier at LDD region but accurate analytical expressions for the drain current Idsat and the transconductance Gmsat in the saturation regime are still not in existence. Recently the drain current dependence of parasitic source resistance Rs has been modeled from the velocity saturation of carriers in LDD region. In this study, we approximate that Rmsat that Rs is linearly dependent on the applied gate voltage. Analytical expressions for Idsat and Gmsat obtained from this approximation show the same general behavior as experimental results of short channel LDD NMOSFETs.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.110.2-110.2
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• 2012

We reported on antireflective ZnSnO (ZTO)/Ag bilayer and ZTO/Ag/ZTO trilayer source/drain (S/D) electrodes for all-transparent ZTO channel based thin film transistors (TFTs). The ZTO/Ag bilayer is more transparent (83.71%) and effective source/drain (S/D) electrodes for the ZTO channel/Al2O3 gate dielectric/ITO gate electrode/glass structure than ZTO/Ag/ZTO trilayer because the bottom ZTO layer in the trilayer increasea contact resistance between S/D electrodes and ZTO channel layer and reduce the antireflection effect. The ZTO based all-transparent TFTs with ZTO/Ag bilayer S/D electrode showed a saturation mobility of 4.54cm2/Vs and switching property (1.31V/decade) comparable to TTFT with Ag S/D electrodes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.239-244
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• 2017

We experimentally investigate the physical mechanism for asymmetrical degradation in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses. The transfer curves exhibit an asymmetrical negative shift after the application of gate-to-source ($V_{GS}$) and drain-to-source ($V_{DS}$) bias stresses of ($V_{GS}=24V$, $V_{DS}=15.9V$) and ($V_{GS}=22V$, $V_{DS}=20V$), but the asymmetrical degradation is more significant after the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20 V) nevertheless the vertical electric field at the source is higher under the bias stress ($V_{GS}$, $V_{DS}$) of (24 V, 15.9 V) than (22 V, 20 V). By using the modified external load resistance method, we extract the source contact resistance ($R_S$) and the voltage drop at $R_S$ ($V_{S,\;drop}$) in the fabricated a-IGZO TFT under both bias stresses. A significantly higher RS and $V_{S,\;drop}$ are extracted under the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20V) than (24 V, 15.9 V), which implies that the high horizontal electric field across the source contact due to the large voltage drop at the reverse biased Schottky junction is the dominant physical mechanism causing the asymmetrical degradation of a-IGZO TFTs under simultaneous gate and drain bias stresses.