• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.481-482
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• 2006

We fabricated pentacene organic thin film transistor with good uniformity. And we extracted contact resistance in organic thin film transistors from the plot of the inverse of drain current versus channel length by extrapolating the curve to a channel length of zero, and multiplying by drain-source voltage. Extracted contact resistance is about $70K{\Omega}$ at gate-drain voltage of -20 V

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.46-52
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• 2012

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

• Proceedings of the Korean Geotechical Society Conference
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• 1996.10a
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• pp.149-158
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• 1996

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.199-200
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• 2005

In this paper, the electrical characteristics and hot-carrier induced electrical performance degradations of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated. Different from the low voltage CMOS device, the only specific on-resistance was degraded due to hot-carrier stressing in LDMOS transistor. However, other electrical parameters such as threshold voltage, transconductance, and saturated drain current were not degraded after stressing. The amount of on-resistance degradation of LDMOS transistor that was implanted n-well with $1.0\times10^{13}/cm^2$ was approximately 1.6 times more than that of LDMOS transistor implanted n-well with $1.0\times10^{12}/cm^2$. Similar to low voltage CMOS device, the peak on-resistance degradation in LDMOS device was observed at gate voltage of 2.2V while the drain applied voltage was 50V. It means that the maximum impact ionization at the drain junction occurs at the gate voltage of 2.2V applying the drain voltage of 50V.

• Magazine of the Korean Society of Agricultural Engineers
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• v.42 no.4
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• pp.115-123
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• 2000

This study compared the degree of consolidation by hyperbolic, curve fitting , Asaoka's and methods using values measured with a theoretical curve in consideration of smear effect and well resistance. The degree of consolidation by the Hyperboilc method was underestimated than the degree of consolidation by Curve fitting. Asaoka's , and Monden's methods. The typical range of the coefficient of horizontal consolidation was Ch=(2-3)Cv in the case considering smear effect and well resistance, and Ch =(0.5-2.1) Cv in the case disregarding smear effect and well resistance. The degree of consolidation obtained by ground settlement monitoring was nearly the same value when the coefficient of smear zone permeability by back analysis was shown to be half that of in-situ and the diameter of the smear zone was shown to be double that of mandrel. By increasing the diameter reduction ratio of the drain, the time of consolidation was delayed. The effect of well resistance showed that the case of a small coefficient of permeability was much more than in the case of a large coefficient of permeability . It was recommended that when designing diameter reduction of a drain, well resistance should be considered.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1997.11a
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• pp.451-462
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• 1997

A 2-dimensional numerical analysis is presented for thermal-electron heat conduction effects upon the electron transport and the drain current-voltage characteristics of submicron GaAs MESFETs, based on the use of a nonstationary hydrodynamic transport model. It is shown that for submicron GaAs MESFETs, electron heat conduction effects are significant on their internal electronic properties and also drain current-voltage characteristics. Due to electron heat conduction effects, the electron energy is greatly one-djmensionalized over the entire device region. Also, the drain current decreases continuously with increasing thermal conductivity in the saturation region of large drain voltages above 1 V. However, the opposite trend is observed in the linear region of small drain voltages below 1 V. Accordingly, for a large thermal conductivity, negative differential resistance drain current characteristics are observed with a pronounced peak of current at the drain voltage of 1 V. On the contrary, for zero thermal conductivity, a Gunn oscillation characteristic is observed at drain voltages above 2 V under a zero gate bias condition.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.309-312
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• 2003

In this study, the electrical characteristic of Symmetric high voltage MOSFET (SHVMOSFET) for display driver IC were investigated. Measurement data are taken over range of temperature (300K-400K) and various extended drain length. In high temperature condition(>400K), drain current decreased over 20％, and specific on-resistance increased over 30％ in comparison with room temperature.

• Proceedings of the Korean Geotechical Society Conference
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• 2007.09a
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• pp.373-382
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• 2007

In the vertical drain method, discharge capacity is generally one of the most important factor which affect on the estimation of the drain efficiency. However, adopting the drain considering discharge capacity only is not sufficiently considered method so that systematic criteria for adoption is necessary to choose the most suitable drain. Therefore, this study represents the application method considering behavior of the ground and vertical drain which is coupled together and ground improvement efficiency analyzing various cases of discharge capacity test performed in the recent soft ground improvement projects. According to the analysis, most drains tend to satisfy the required discharge capacity. It presents that deformed shape of the drains and well resistance estimation along the ground settlement, improvement efficiency by water content ratio along the depth and shear strength obtained after ground improvement should be considered altogether with the discharge capacity to select the proper drain. Also, appropriate adoption of drain material considering the ground condition is vital through analyzing the field measured data and comparing the result of the discharge capacity test as various vertical drain materials are being constructed continuously.

• Transactions on Electrical and Electronic Materials
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• v.17 no.3
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• pp.143-145
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• 2016

In order to find suitable source and drain (S/D) electrodes for amorphous InGaZnO thin film transistors (a-IGZO TFTs), the specific contact resistance of interface between the channel layers and various S/D electrodes, such as Ti/Au, a-IZO and multilayer of a-IGZO/Ag/a-IGZO, was investigated using the transmission line model. The a-IGZO TFTs with a-IGZO/Ag/a-IGZO of S/D electrodes had good performance and low contact resistance due to the homo-junction with channel layer. The stability was measured with different electrodes by a positive bias stress test. The result shows the a-IGZO TFTs with a-IGZO/Ag/a-IGZO electrodes were more stable than other devices.