• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2014.11a
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• pp.108-109
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• 2014

본 논문에서는 gate와 drain bias stress하에서의 a-IGZO thin-film transistors (TFTs)의 비대칭 열화 메커니즘 분석을 진행하였다. Gate와 drain bias stress하에서의 a-IGZO TFT의 열화 현상은 conduction band edge 근처에 존재하는 oxygen vacancy-related donor-like trap의 발생으로 예상되며, TFT의 channel layer 내에서의 비대칭 열화현상은 source의 metal과 a-IGZO layer간의 contact에 전압이 인가되었을 경우, reverse-biased Schottky diode에 의한 source 쪽에서의 높은 electric field가 trap generation을 가속화시킴으로써 일어나는 것임을 확인할 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.2
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• pp.104-110
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• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1997.11a
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• pp.451-462
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• 1997

A 2-dimensional numerical analysis is presented for thermal-electron heat conduction effects upon the electron transport and the drain current-voltage characteristics of submicron GaAs MESFETs, based on the use of a nonstationary hydrodynamic transport model. It is shown that for submicron GaAs MESFETs, electron heat conduction effects are significant on their internal electronic properties and also drain current-voltage characteristics. Due to electron heat conduction effects, the electron energy is greatly one-djmensionalized over the entire device region. Also, the drain current decreases continuously with increasing thermal conductivity in the saturation region of large drain voltages above 1 V. However, the opposite trend is observed in the linear region of small drain voltages below 1 V. Accordingly, for a large thermal conductivity, negative differential resistance drain current characteristics are observed with a pronounced peak of current at the drain voltage of 1 V. On the contrary, for zero thermal conductivity, a Gunn oscillation characteristic is observed at drain voltages above 2 V under a zero gate bias condition.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.4
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• pp.59-64
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• 2016

In this paper, a 10W GaN MMIC was designed and fabricated using the Ku-band SSPA module. For Design and fabrication of the SSPA module using Rogers(RO4003C) substrate was used for Branch-line structure. SSPA modules on budget Divider/Combiner was designed and fabricated less than the maximum insertion loss - 0.7dB. In addition, because it must be applied to the structural nature of GaN MMIC Gate Bias-Drain Bias circuit was implemented to apply the Gate-Drain sequential circuit, implemented the RF Power Detect, Temperature Detect, HPA On/Off function. Design and fabrication Ku-band SSPA Module got the measurement results that satisfy a maximum output of 15.6W, Gain 45.7dB, 19.0% efficiency.

• Proceedings of the KIEE Conference
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• 1988.11a
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• pp.363-367
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• 1988

A simple analytical model for the lateral channel electric field in gate - offset structured Lightly Doped Drain MOSFET has been developed. The model's results agree well with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field as function of drain and gate bias conditions and process, design parameters. Advantages of analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate / drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot - electron phenomena, individually. We are able to find the optimum doping concentration of LDD minimizing the peak electric field and hot - electron effects.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.71-78
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• 1994

We have developed GaAs power metal semiconductor field effect transistors (MESFETs) for 4.7V operation under 900 MHz using a low-high deped structures grown by molecular beam epitaxy (MBE). The fabricted MESFETs with a gate widty of 7.5 mm and a gate length of 1.0.mu.m show a saturated drain current (Idss) of 1.7A and an uniform transconductance (Gm) of around 600mS, for gate bias ranged from -2.4 V to 0.5 V. The gate-drain breakdown voltage is measured to be higher than 25 V. The measured rf characteristics of the MESFETs at a frequency of 900 MHz are the output power of 31.4 dBm and the power added efficiency of 63% at a drain bias of 4.7 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.94-100
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• 2017

Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (${\Delta}L_{ch}$) and threshold voltage shift (${\Delta}V_{th}$). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.918-923
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• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.485-489
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• 2015

An accurate large-signal BSIM4 macro model including new empirical bias-dependent equations of the drain-source capacitance and channel resistance constructed from bias-dependent data extracted from S-parameters of RF MOSFETs is developed to reduce $S_{22}$-parameter error of a conventional BSIM4 model. Its accuracy is validated by finding the much better agreement up to 40 GHz between the measured and modeled $S_{22}$-parameter than the conventional one in the wide bias range.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.367-372
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• 1999

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.