• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.180-183
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• 2000

Beginning with a brief introduction on near 100 nm or below CMOS devices, this paper addresses novel devices for future sub-100 nm CMOS. First, key issues such as gate materials, gate dielectric, source/drain, and channel in Si bulk CMOS devices are considered. CMOS devices with different channel doping and structure are introduced by explaining a figure of merit. Finally, novel device structures such as SOI, SiGe, and double-gate devices will be discussed for possible candidates for sub-100 nm CMOS.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.41-44
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• 2001

In this paper, we explain briefly polysilicon guard layer in a simple 3-D structure. Simulation was performed extensively to see interference and characterize the role of the polysilicon guard layer. Especially, we performed extensively S-parameter simulation to analysis the signal interference. The interference was characterized in terms of oxide thickness, polysilicon doping concentration, thickness, number of contact of polysilicon guard, and metal guard size.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.22-24
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• 1995

The electrical conductivity of TiO$_2$doped ZnO was investigated by means of complex impedance measurement and voltage-current source and meaurement unit. The e1ectrical conductivity of TiO$_2$added ZnO was increased with increasing the concentration of TiO$_2$. The calculated relative dielectric constant was decreased with increasing the concentration of TiO$_2$. The increase of electrical conductivity seems to be the effect of TiO$_2$donor doping.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.448-449
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• 2008

HIT(Heterojunction with intrinsic thin layer) solar cell은 결정 실리콘 (c-Si)을 n-type으로 제작시 수율이 어렵고 결정 실리콘 (c-Si)을 p-type위에 제조하는 것이 보다 보편적인 방법이므로 베이스의 결정 실리콘에는 p-type을, 그 위에는 진성 층(intrinsic layer) 그리고 반투명 전극의 아래에 제조되는 비정질 실리콘 (a-Si)을 n-type으로 하여 베이스 층과 TCO 후면 층의 두께, 도핑 농도 (doping concentration)와의 관계를 확인하여 본다.

• 한국전기화학회:학술대회논문집
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• 2001.04a
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• pp.54-54
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• 2001

• Transactions on Electrical and Electronic Materials
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• v.13 no.5
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• pp.241-244
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• 2012

Antimony doped tin oxide (ATO) thin films on glass substrate were prepared by the chemical solution deposition (CSD) method, using sol-gel solution synthesized by non-alkoxide precursors and the sol-gel route. The crystallinity and electrical properties of ATO thin films were investigated as a function of the annealing condition (both annealing environments and temperatures), and antimony (Sb) doping concentration. Electrical resistivity, carrier concentration, Hall mobility and optical transmittance of ATO thin films were improved by Sb doping up to 5~8 mol% and annealing in a low vacuum atmosphere, compared to the undoped tin oxide counterpart. 5 mol% Sb doped ATO film annealed at $550^{\circ}C$ in a low vacuum atmosphere showed the highest electrical properties, with electrical resistivity of about $8{\sim}10{\times}10^{-3}{\Omega}{\cdot}cm$, and optical transmittance of ~85% in the visible range. Our research demonstrates the feasibility of low-cost solution-processed transparent conductive oxide thin films, by controlling the appropriate doping concentration and annealing conditions.

• Transactions on Electrical and Electronic Materials
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• v.14 no.3
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• pp.148-151
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• 2013

The control of Ga doping in ZnO nanowires (NWs) by physical vapor deposition has been implemented and characterized. Various Ga-doped ZnO NWs were grown using the vapor-liquid-solid (VLS) method, with Au catalyst on c-plane sapphire substrate by hot-walled pulsed laser deposition (HW-PLD), one of the physical vapor deposition methods. The structural, optical and electrical properties of Ga-doped ZnO NWs have been systematically analyzed, by changing Ga concentration in ZnO NWs. We observed stacking faults and different crystalline directions caused by increasing Ga concentration in ZnO NWs, using SEM and HR-TEM. A $D^0X$ peak in the PL spectra of Ga doped ZnO NWs that is sharper than that of pure ZnO NWs has been clearly observed, which indicated the substitution of Ga for Zn. The electrical properties of controlled Ga-doped ZnO NWs have been measured, and show that the conductance of ZnO NWs increased up to 3 wt% Ga doping. However, the conductance of 5 wt% Ga doped ZnO NWs decreased, because the mean free path was decreased, according to the increase of carrier concentration. This control of the structural, optical and electrical properties of ZnO NWs by doping, could provide the possibility of the fabrication of various nanowire based electronic devices, such as nano-FETs, nano-inverters, nano-logic circuits and customized nano-sensors.

• Transactions on Electrical and Electronic Materials
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• v.8 no.2
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• pp.73-78
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• 2007

The crystallization temperature in GeTe solid electrolyte films was improved by in situ-nitrogen doping by rf magnetron co-sputtering technique at room temperature. The crystallization temperature of $250\;^{\circ}C$ in electrolyte films without nitrogen doping increased by approximately $300\;^{\circ}C$, $350\;^{\circ}C$, and above $400\;^{\circ}C$ in films deposited with nitrogen/argon flow ratios of 10, 20, and 30 %, respectively. A PMC memory device with $Ge_{45}Te_{55}$ solid electrolytes deposited with nitrogen/argon flow ratios of 20 % shows reproducible memory switching characteristics based on resistive switching at threshold voltage of 1.2 V with high $R_{off}/R_{on}$ ratios. Nitrogen doping into the silver saturated GeTe electrolyte films improves the crystallization temperature of electrolyte films and does not appear to have a negative impact on the switching characteristics of PMC memory devices.

• 한국태양에너지학회:학술대회논문집
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• 2011.04a
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• pp.101-104
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• 2011

Many studies in crystalline silicon solar cell fabrication have been focused on high efficiency and low cost. In this paper, we carried out the doping procedure by varying the silicon wafer thicknesses and sheet resistance. The silicon wafers with various thicknesses were obtained by shiny etching and texturing. The thicknesses of wafers were 100, 120, 150, and $180{\mu}m$. The emitter layer formed by $POCl_3$ doping process had sheet resistance with 40 and $80{\Omega}/sq$ for selective emitter application. This experiment indicated wafer thickness did not influence sheet resistance but lifetime was strongly effected.

• Journal of the Korean Ceramic Society
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• v.29 no.10
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• pp.822-826
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• 1992

SiO2 doped sapphire single crystals were grown by Verneuil method using feed material which prepared by adding SiO2 in Al2O3. Crystal growing were attempted with varing doping amount of SiO2 from 0.01 to 1.0 wt% and when the doping amount of SiO2 were 0.01~0.04 wt%, single crystals could be attained. Starting materials for feed powder were 99.99% purity alumina and extra pure SiO2 powder. Mixing these two materials by wet milling for 24 hours and drying the mixture and then was calcined at 900~110$0^{\circ}C$ for 2~4 hours. The grown crystals had yellowish color and were somewhat transparent. During growing process the flow range of oxygen was 5~7.5ι/min and of hydrogen was 13~25ι/min, the average growth rate was 7.0~11 mm/hr. The pressure of gases were fixed at 5psi. The color of crystal was appeared and mechanical property of sapphire was developed by doping of SiO2.