• Proceedings of the KSR Conference
• /
• 2004.10a
• /
• pp.1341-1346
• /
• 2004

Basic design for single-phase active power filter, which aims at railway applications provided with PWM-controlled converters, is comprehensively studided and its performance is presented in this paper, Active power filters are used to compensate railway signaling and public telecommunication interference due to the high-order harmonic currents generated in railway traction locomotives. A type of hybrid digital filter which is composed of low pass filter and high pass filter is proposed so that the desired harmonic reference current with accurate magnitude and phase shift can be extracted from catenary line current. A design criteria to determine input inductor L and output capacitor C is also described, considering voltage, current. PWM pattern, and switching frequency of the main converters, Finally, computer simulation and DSP-based experiments resulted from laboratory test are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.92-97
• /
• 2009

Low power consumption is crucial for medical implantable devices. A low-power 4th-order band-pass Gm-C filter with distributed gain stage for the sensing stage of the implantable cardiac pacemaker is proposed. For the implementation of large-time constants, a floating-gate operational transconductance amplifier with current division is employed. Experimental results for the filter have shown a SFDR of 50 dB. The power consumption is below $1.8{\mu}W$, the power supply is 1.5 V, and the core area is $2.4\;mm{\times}1.3\;mm$. The filter was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.48 no.2
• /
• pp.63-68
• /
• 1999

This pper describes a digital sensorless drive of permanent magnet brushless DC motors. In order to detect in real time the rotor positions of which Emf becomes zero, terminal voltages are sampled during PWM duty cycle. This method generates detection error in indirect sensed position, which is the harmonic component of PWM frequency. In this paper, the drive adopted Butterworth low pass filter for rejection of the sensing error and for accurate estimation of commutation time. Analytical design process of the digital filter is proposed and the experimental results show that the performance of the proposed sensorless drive is superior to that of the sensorless drives without filterint.

• International journal of advanced smart convergence
• /
• v.4 no.2
• /
• pp.138-144
• /
• 2015

Digital filters are extensively used in the world of communication. In order to design a digital finite impulse response (FIR) filter that satisfies all the required conditions is challenging. In this paper, design techniques of digital low pass FIR filters using Rectangular window method, Hamming window, Hanning window, and Optimal Parks McClellan method are presented. The stability, number of components required and filter coefficients are demonstrated for different design techniques. It is demonstrated that filter design using hamming window is comparatively better than rectangular and hanning window though the components required for all of the windowing technique are same, hamming shows higher stability. The stability is shown with the help of magnitude and phase spectrum of each window. Simulation is carried out using MATLAB and comparisons are made entirely based on the output of the simulation.

• Proceedings of the KIEE Conference
• /
• 1993.07a
• /
• pp.447-449
• /
• 1993

Digital filter is a signal processor which converts the sequence input sampled from analog signal into another sequence output. It includes software routines which filter digital signal, a computer system for executing the routines, and a data acquisition system which implements A/D, D/A signal conversion. In this paper, a data acquisition system is designed and implemented for one-board computer of MC68000. Also, the theory regarding signal conversion and and its problems occured in implementation are considered. And then, with the hardware implemented like this, design of a digital low-pass filter with the cutoff frequency of 200Hz is implemented, and related characteristics are considered.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.3
• /
• pp.438-445
• /
• 2017

This paper presents a low-power high-resolution band-pass ${\Sigma}{\Delta}$ ADC for accelerometer applications. The proposed band-pass ${\Sigma}{\Delta}$ ADC consists of a high-performance 6-th order feed-forward ${\Sigma}{\Delta}$ modulator with 1-bit quantization and a low-power, area-efficient digital filter. The ADC is fabricated in 180 nm 1P6M mixed-signal CMOS process with a die area of $5mm^2$. This high-resolution ADC got 90 dB peak signal to noise plus distortion ratio (SNDR) and 96 dB dynamic range (DR) over 4 kHz bandwidth, while the intermediate frequency (IF) is shifting from 100 KHz to 200 KHz. The power dissipation of the chip is 5.6 mW under 1.8 V (digital)/3.3 V (analog) power supply.

• Transactions of the Korean Society of Automotive Engineers
• /
• v.22 no.6
• /
• pp.23-30
• /
• 2014

This paper proposes a dead time compensation method for an AC motor drive using phase current polarity information which is detected based on a digital programmable low-pass filter (PLPF). The polarity detection using the PLPF is an alternative solution of a conventional method which uses a general low-pass filter (LPF) and hysteresis bands in order to avoid jittering due to noises. The PLPF not only adjusts its cutoff frequency according to the synchronous frequency of AC motors but also eliminates a gain attenuation and phase delay which are main problems of the general LPF. Through the PLPF, a fundamental component signal without gain and phase distortions is extracted from the measured raw current signal with noise. By use of the fundamental component, the polarity of current is effectively detected by reducing the hysteresis band. Finally, the proposed method compensates the dead time effects by adding or subtracting average voltage value to voltage references of the controller according to the detected current polarity information. The proposed compensation method is experimentally verified by compared with the conventional method.

• Proceedings of the KIEE Conference
• /
• 1996.07a
• /
• pp.553-555
• /
• 1996

This paper concerns with a method to improve the current and power waveforms of the variable speed $3{\Phi}$ AC motor system driven by the single-pulse PWM, and the current waveforms and $3{\Phi}$ power waveforms are analyzed by FFT under various running conditions. By the performance analysis through the experiments, the following results have been obtained. AC source of pseudo sine waveform can be obtained from the modulated alternating square voltage by means of the well designed LC filter. It is confirmed that current waveforms and $3{\Phi}$ power waveforms can be improved by utilizing the high order low pass LC filter than that of lower order. Especially, current waveforms and $3{\Phi}$ power waveforms tan be much improved at low frequency domain. $3{\Phi}$ power waveforms have a smatter ripple and bigger power by utilizing the high order low pass LC filter than that of lower order. Also, the running condition of $3{\Phi}$ AC motor is good at low frequency domain.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.4
• /
• pp.879-885
• /
• 2004

This paper describes an adaptive signal processing of digital receiver with digital down convertor(DDC). DDC is composed of numerically controlled oscillator(NCO) and digital low pass filler and the received signal is processed by numerical algorithm. The simulation results of digital receiver using the passband sampling technique are presented and we confirmed that the received low IF signal is converted to zero IF by numerically processed DDC. Direction of arrival(DOA) estimation technique using multiple signal classification(MUSIC) algorithm with high resolution is also discussed. We knew that an accurate resolution of DOA depends on the input sampling numbers and antenna element numbers.

• Proceedings of the KIPE Conference
• /
• 2004.07b
• /
• pp.787-790
• /
• 2004

In this paper, a novel control scheme compensating for source voltage unbalance and current harmonics and power factor correction in unified active power filter systems combined with shunt passive filters is proposed, where no low/high-pass filter are used in deriving the reference voltage for compensation. Using digital all-pass filters, the phase angle and the reference voltages compensating for harmonic current and unbalanced voltage are derived from the positive sequence component of the unbalanced voltage. The amplitude of d-axis current in a series filter is controlled as zero for power factor correction. The validity of the proposed control scheme has been verified by experimental results.