• ETRI Journal
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• v.30 no.5
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• pp.744-746
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• 2008

This letter presents a crosstalk-enhanced polymer thermo-optic digital optical switch operating at a low power consumption. Modified radiation-type attenuators are integrated in a series with a conventional $1{\times}2$ digital optical switch. A low optical crosstalk of less than -45 dB is attained at a low applied switching power of 60 mW, and an insertion loss of about 1.1 dB is exhibited.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1A
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• pp.28-34
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• 2011

In this paper, we proposed the architecture of the Hybrid Quadrature Polar transmitter which has the wideband characteristics available for the SRD(Short Range Device). First, we developed the simulation environment and carried out performance degradation analysis. Second, we considered the slewrate of the VVA(Voltage Variable Attenuator), time delay between magnitude signal and phase signal and the number of bits for DAC(Digital-to-Analog Converter) as the main performance factors. Then we obtained the minimum required values to meet the transmitting performance requirements of 3GPP standards through simulation results. Based on these results, we implemented the Wideband Hybrid Quadrature Polar transmitter platform and varified the performance requirements through practical measurement.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.586-589
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• 2003

Repeater is developed. Based on the systems The up-converter of the WCDMA Digital Optic pecifications, the structure of the up-converter is accomplished and its block diagram is drawn. The up-converter is implemented according to these block diagrams. Subsequently the low pass filter, the automatic level controlled attenuator, the frequency synthesizer and other components for the up-converter are designed and implemented, and a main board to integrate these modules is also manufactured. To reduce the noise floor of system and suppress the RF spurious noise, a PCB layout is performed carefully. For each module consisting of the up-converter and the entire system, the performance tests are accomplished to check the performance about the specifications.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.215-216
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• 2006

In this paper, the antenna the with linear active phased array of $1{\times}16$ operated in DBS band was designed. The antenna was composed of sixteen radiating elements, sixteen active channels and five Wilkinson power combiners with 4-channel inputs, a digital control board and a stabilizing DC bias board. The radiating element of the array has the structure of a microstrip stack patch with a left-hand circular polarization. And, each active channel consists of a low noise ampilifier, a 3-bit digital phase shifter and a variable analog attenuator. The breadboard of linear active phased array antenna was also fabricated to test the electrical performances. The radiation patterns of the antenna were measured after correcting initial phases of each active channel in aechoic chamber. And also, the beam scanning chracteristcs of $10^{\circ}$, $20^{\circ}$, $30^{\circ}$ were measured.

• ETRI Journal
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• v.35 no.3
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• pp.378-385
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• 2013

An S-band multifunction chip with a simple interface for an active phased array base station antenna for next-generation mobile communications is designed and fabricated using commercial 0.5-${\mu}m$ GaAs pHEMT technology. To reduce the cost of the module assembly and to reduce the number of chip interfaces for a compact transmit/receive module, a digital serial-to-parallel converter and an active bias circuit are integrated into the designed chip. The chip can be controlled and driven using only five interfaces. With 6-bit phase shifting and 6-bit attenuation, it provides a wideband performance employing a shunt-feedback technique for amplifiers. With a compact size of 16 $mm^2$ ($4mm{\times}4mm$), the proposed chip exhibits a gain of 26 dB, a P1dB of 12 dBm, and a noise figure of 3.5 dB over a wide frequency range of 1.8 GHz to 3.2 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.7
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• pp.571-575
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• 2017

This paper presents a C-band bi-directional T/R chipset in $0.13{\mu}m$ TSMC CMOS technology for phased array antenna. The T/R chipset, which is a key component of phased array antenna, consists of a 6 bit phase shifter, a 6 bit step attenuator, and three bi-directional gain amplifiers. The phase shifter is controlled up to $354^{\circ}$ with $5.625^{\circ}$ phase step for precise beam steering. The step attenuator is also controlled up to 31.5 dB with 0.5 dB attenuation step for the side lobe level rejection. The LDO(Low Drop Output) regulator for stable 1.2 V DC power and the SPI(Serial Peripheral Interface) for digital control are integrated in the chipset. The chip size is $2.5{\times}1.5mm^2$ including pads.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.974-978
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• 2003

The down-converter of the WCDMA Digital Optic Repeater is developed. Based on the system specifications, the structure of the down-converter is accomplished and its block diagram is drawn. The down-converter is implemented according to these block diagrams. Subsequently a low pass filter, an automatic level controlled attenuator, a frequency synthesizer and other components for the down-converter are designed and implemented, and a main board to integrate these modules is also manufactured. To reduce the noise floor of system and suppress the RF spurious noise, a PCB layout is performed carefully. For each module consisting of the down-converter and the entire system, the performance tests are accomplished to check the performance about the specifications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.6
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• pp.900-909
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• 1999

The receiving part of the RF system for the digital TRS base stations is developed in this paper. Based on the system specifications, the structure of the RF system is accomplished and its block diagram is drawn. The RF system is implemented according to these block diagrams. Subsequently the RF band-pass filter, the low noise amplifier, the automatic level controlled attenuator, the frequency synthesizer and other components for the system are designed and implemented, and a main board to integrate these modules is also manufactured. To lower the noise floor of the system and suppress the RF spurious noise, a PCB layout is performed carefully. For each module consisting of the RF system and the entire system, the performance tests are accomplished to check the specifications.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.6-13
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• 2009

For X-band phased array systems, a power amplifier, a 6-bit phase shifter, a 6-bit digital attenuator, and a SPDT transmit/receive (T/R) switch are fabricated and measured. All circuits are demonstrated by using CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascade structures. It provides 1-dB gain-compressed output power ($P_{1dB}$) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8-11 GHz frequencies. The 6-bit phase shifter utilizes embedded switched filter structure which consists of nMOS transistors as a switch and meandered microstrip lines for desired inductances. It has $360^{\circ}$ phase-control range and $5.6^{\circ}$ phase resolution. At 8-11 GHz frequencies, it has RMS phase and amplitude errors are below $5^{\circ}$ and 0.8 dB, and insertion loss of $-15.7\;{\pm}\;1,1\;dB$. The 6-bit digital attenuator is comprised of embedded switched Pi-and T-type attenuators resistive networks and nMOS switches and employes compensation circuits for low insertion phase variation. It has max. attenuation of 31.5 dB and 0.5 dB amplitude resolution. Its RMS amplitude and phase errors are below 0.4 dB and $2^{\circ}$ at 8-11 GHz frequencies, and insertion loss is $-10.5\;{\pm}\;0.8\;dB$. The SPDT T/R switch has series and shunt transistor pairs on transmit and receive path, and only one inductance to reduce chip area. It shows insertion loss of -1.5 dB, return loss below -15 dB, and isolation about -30 dB. The fabricated chip areas are $1.28\;mm^2$, $1.9mm^2$, $0.34\;mm^2$, $0.02mm^2$, respectively.