• 전자공학회논문지D
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• 제34D권7호
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• pp.23-29
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• 1997

The performance degradation of CMOS differential amplifiers due to hot carrier effect has been measured and analyzed. Two-state CMOS amplifiers whose input transistors are PMOSFETs were designed and fabriacted using the ISRC CMOS 1.5.mu.m process. It was observed after the amplifier was hot-carrier stressed that the small-signal voltage gain and the input offset voltage increased and the phase margin decreased. The performance variation results from the increase of the transconductances and gate capacitances of the PMOSFETs used as input transistors in the differential input stage and the output stage and also resulted from the decrease of their output conductances. After long-term stress, the amplifier became unstable. The reason might be that its phase margin was reduced due to hot carrier effect.

• 한국전자파학회논문지
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• 제14권8호
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• pp.891-897
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• 2003

본 논문에서는 원형의 직교편광기를 새로이 제작하여 무선광 차동검출기를 구성하고 잡음광 소거에 활용하였다. 직교편광기는 2개의 반원형 편광기의 통과축이 서로 수직이 되도록 접합하여 1개의 원형을 이루며, 이를 모터로 구동하여 신호광의 편파와 매칭을 시킴으로써 잡음광의 간섭을 소거하였다. 적외선 광필터가 부착된 단일의 포토트랜지스터를 사용할 때에 비하여 직교편광기를 사용한 차동검출기에서 잡음의 세기가 약 20 dB 감소하였다.

• 대한전기학회논문지:전력기술부문A
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• 제53권4호
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• pp.214-220
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• 2004

This paper describes a busbar current differential relay in conjunction with a current transformer(CT) compensating algorithm irrespective of the level of the remanent flux. The compensating algorithm detects the start of first saturation if the third-difference function of the current exceeds the threshold; it estimates the core flux at the first saturation start by inserting the negative value of the third-difference function of the current into the magnetization curve; thereafter, it calculates the core flux during the fault and compensates the distorted current using the magnetization curve. The algorithm estimates the correct secondary current irrespective of the level of the remanent flux and needs no saturation point of the magnetization curve. The proposed relay can improve not only security of the relay on an external fault with CT saturation but sensitivity of the relay on an internal fault; the relay can improve the operating speed on n internal fault with CT saturation. This paper concludes by implementing the relay into a digital signal processor based prototype relay.

• Journal of electromagnetic engineering and science
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• 제8권4호
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• pp.153-157
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• 2008

Most of malfunctions in electronic equipment or systems controlled by processors is occurred by the differential- and common-mode noises, and the electrical fast transient (EFT). The International Electrotechnical Commission (IEC) has prepared the dummy signal to test the immunity level of the equipment. For the countermeasure against the differential- and common-mode noises, and the EFT, we designed, fabricated, and tested a new electromagnetic compatibility (EMC) filter, which is composed of feed-through capacitors and ferrite beads with high permeability. As a result, the filter showed excellent differential- and common-mode noises filtering, and immunity improving characteristics over the frequency band from 30 MHz to 1.5 GHz and 1.8 GHz, respectively.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제53권4호
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• pp.214-214
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• 2004

This paper describes a busbar current differential relay in conjunction with a current transformer(CT) compensating algorithm irrespective of the level of the remanent flux. The compensating algorithm detects the start of first saturation if the third-difference function of the current exceeds the threshold; it estimates the core flux at the first saturation start by inserting the negative value of the third-difference function of the current into the magnetization curve; thereafter, it calculates the core flux during the fault and compensates the distorted current using the magnetization curve. The algorithm estimates the correct secondary current irrespective of the level of the remanent flux and needs no saturation point of the magnetization curve. The proposed relay can improve not only security of the relay on an external fault with CT saturation but sensitivity of the relay on an internal fault; the relay can improve the operating speed on n internal fault with CT saturation. This paper concludes by implementing the relay into a digital signal processor based prototype relay.

• 대한전기학회논문지:전력기술부문A
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• 제52권3호
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• pp.158-164
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• 2003

This paper proposes a percentage current differential relaying algorithm for bus protection using an advanced compensating algorithm of the secondary current of current transformers (CTs). The compensating algorithm estimates the core flux at the start of the first saturation based on the value of the second-difference of the secondary current. Then, it calculates the core flux and compensates distorted currents using the magnetization curve. The algorithm Is unaffected by a remanent flux. The simulation results indicate that the proposed algorithm can discriminate internal faults from external faults when the CT saturates. This paper concludes by implementing the algorithm into a TMS320C6701 digital signal processor. The results of hardware implementation are also satisfactory. The proposed algorithm can improve not only stability of the relay in the case of an external fault but sensitivity of the relay in the case of an internal fault.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.587-590
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• 2000

For high-accuracy signal processing of differential capacitance transducers, an interface circuitry based on a switched-capacitor sample/hold circuit is developed. Driven by nonoverlapping two-phase clocks, the interface produces the output voltage which is proportional to the ratio of difference-to-sum of two capacitors of a differential transducer. Performances of a prototype chip fabricated using 0.6 $\mu\textrm{m}$ n-well CMOS process were measured and compared with those simulated by HSPICE. The measured results indicate that 0.1% resolution is achievable with the proposed interface and the temperature-dependence of the interface is small enough fur practical applications.

• 유체기계공업학회:학술대회논문집
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• 유체기계공업학회 2003년도 유체기계 연구개발 발표회 논문집
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• pp.562-567
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• 2003

This paper presents the method of Rate of Loading(ROL) improvement for the Motor Operated Gate Valve operating in high differential pressure condition. The character of ROL and Stem Factor is analyzed. Static test and dynamic test were performed and acquired the diagnosis signal for the valve closing stroke. The result of this study is the modification of stem factor is very important factor for the ROL improvement. In order to obtain the same value of dynamic test thread friction coefficient stem and stem nut should be combined appropriately.

• ETRI Journal
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• 제43권4호
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• pp.746-757
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• 2021

Side-channel attacks pose an inevitable challenge to the implementation of cryptographic algorithms, and it is important to mitigate them. This work identifies a novel data encoding technique based on 1-of-4 codes to resist differential power analysis attacks, which is the most investigated category of side-channel attacks. The four code words of the 1-of-4 codes, namely (0001, 0010, 1000, and 0100), are split into two sets: set-0 and set-1. Using a select signal, the data processed in hardware is switched between the two encoding sets alternately such that the Hamming weight and Hamming distance are equalized. As a case study, the proposed technique is validated for the NIST standard AES-128 cipher. The proposed technique resists differential power analysis performed using statistical methods, namely correlation, mutual information, difference of means, and Welch's t-test based on the Hamming weight and distance models. The experimental results show that the proposed countermeasure has an area overhead of 2.3× with no performance degradation comparatively.

• KEPCO Journal on Electric Power and Energy
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• 제6권4호
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• pp.473-480
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• 2020

In this paper, we proposed a high frequency equivalent circuit considering parasitic impedance components for differential noise analysis on the input stage during DC-DC buck converter switching operation. Based on the proposed equivalent circuit model, we presented a method to measure parasitic impedance parameters included in DC bus plate, IGBT, and PCB track using the gain phase method of a network analyzer. In order to verify the validity of this model, a DC-DC prototype consisting of a buck converter, a signal analyzer, and a LISN device, and then resonance frequency was measured in the frequency range between 150 kHz and 30 MHz. The validity of the parasitic impedance measurement method and the proposed equivalent model is verified by deriving that the measured resonance frequency and the resonance frequency of the proposed high frequency equivalent model are the same.