• 한국재료학회지
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• 제3권1호
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• pp.19-27
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• 1993

RF magnetrom sputtering으로 52/48 PZT target을 사용하여 PZT thin film을 증착시킨후, furnace annealing을 실시하여 Si 기판에서는 55$0^{\circ}C$에서부터 안정상인 peroskite구조가 형성되었다. Si기판위에서는 후속열처리시 계면에 상당한 산화막층이 형성되었으며 TiN 기판위에서는 후속열처리시 TiN층은 사라지고 Ti$O_2$층이 형성되었다. Si$O_2$기판에서는 후속열처리후에도 안정한 PZT film을 형성시킬 수 있었다. As-depo.시에는 PZT film의 조성비가 균일하게 유지되었으나 75$0^{\circ}C$후속열 처리시에는 상당량의 Pb가 Si기판으로 diffusion하였으며 Si도 out-diffusion하였다. 전기적 특성은 10KHz에서 C-V를 측정결과 약 1300정도의유전상수 값이 나왔으나 후속열처리시 표면에 crack이 발생하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1487-1489
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• 2001

The tantalum oxide($Ta_2O_5$) is an important material for present thin-film capacitor application owing to its high dielectric constant and thermal stability. We report dielectric property of Si(p type)/Pt/$Ta_2O_5$/Ag based MIM structure obtained by RF sputtering and annealed in vacuum environment. We have measured and researched the characteristics of C-F, C-V and EPMA. And we describe parameter dependence on sputtered condition and annealed temperature with dielectric property.

• 대한전자공학회논문지TE
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• 제42권4호
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• pp.1-6
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• 2005

최근 저항이나 캐패시터와 같은 수동소자를 PCB의 내층에 제조하는 임베디드 패시브 기술이 고성능의 IT 제품을 제조하는데 사용되고 있다. 그런데 임베디드 캐패시터는 정전용량 밀도가 낮아 회로소자로서의 전반적인 응용에 한계가 있다. 본 논문에서는 이러한 한계를 극복하기 위하여 wrinkle형의 전극과 유전체 층을 가진 새로운 임베디드 캐패시터를 제안하였다. FEM 기법을 사용하여 wrinkle형 임베디드 캐패시터의 정전용량 밀도를 평가하였다. Wrinkle형 임베디드 캐패시터는 기존의 평면형 임베디드 캐패시터에 비하여 25.6%$\sim$39.6% 정도 큰 정전용량 밀도를 나타내었다. 특히, thin film형 임베디드 캐패시터에 wrinkle 구조를 적용할 때 정전용량 밀도가 보다 많이 향상되었다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.586-589
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• 2012

In this paper, a tunable capacitor like an interdigital one is presented for low-voltage applications. In order to reduce operation voltage by enhancing fringing electric fields, two finger-patterned electrodes are vertically separated by employing a multi-layer thin film dielectric of a para-/ferro-/para-electrics without spacing between electrodes. The proposed tunable capacitor was fabricated on a quartz wafer and its characteristics are analyzed in terms of effective capacitance and tunability with a function of applied voltages, compared to the conventional interdigital capacitor (IDC). At 8V and 2 GHz, the proposed tunable capacitor shows the tunability of 18 % that is 10.3 % higher than that of the compared one.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.58-61
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• 2001

Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.126-129
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• 1999

Dielectric and piezoelectric properties of perovskite materials such as La modified $Pb(Zr,Ti)O_3$ ceramics and $Pb(Zn_{1/3}Nb_{2/3})O_3-PbTiO_3$ single crystals were investigated for cryogenic capacitor and actuator applications. Enhanced extrinsic contributions resulted in piezoelectric coefficient (d33) as high as 250 pC/N at 30 K, superior to that of PZT ($d_{33}$ ~ 100 pC/N). This cryogenic property enhancement was associated with retuning the MPB (or cryogenic temperatures. PZN-PT single crystals exhibited dramatic property improvements such as $d_{33}$ > 500 pC/N at 30 K as a result of an engineered domain state.

• 한국염색가공학회지
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• 제31권2호
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• pp.65-76
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• 2019

A multi-point touch input sensor having different sizes or different capacitance touch points connected by only one pair of signal transmission lines was fabricated using a polyimide film coated with a thin copper plate. The capacitance increases with the decrease in the number of sheets of fabric spacers placed between the two sheets of the polyimide film. Therefore, the touch input sensor could be manufactured without fabric spacers, which was possible by the action of the polyimide film as a dielectric material in the capacitor. On the multi-point touch sensor, higher capacitance was obtained when pressing wider-area touch points with 10mm to 25mm diameter on average. However, the capacitance of a system comprising two sheets of touch sensors was considerably low, causing a serious overlap of the capacitance values according to the data collected from the reliability test. Although the capacitance values could be increased by stacking several sheets of touch sensors, the overlap of data was still observed. After reducing the size of all touch points to 10mm and stacking up to eight sheets of sensors, reliable and consistent capacitance data was obtained. Five different capacitance signals could be induced in the sensors by pushing touch points simultaneously.

• 전자공학회논문지A
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• 제32A권12호
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• pp.101-107
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• 1995

To improve the leakage current, we developed two step sputtering method where PZT thin film in first deposited at room temperature followed by 600.deg. C deposition. The method used an amorphous PZT layer deposited at room temperature to keep a stable interface during sputtering at high temperature. PZT thin films were deposited on Pt/Ti/SiO$_{2}$/Si substrate at room temperature and 600.deg. C sequentially. The effect of the layer deposited at room temperature was investigated with regard to I-V characteristics and P-E hysteresis loop. In the case of the sample with the layer deposited at room temperature, both leakage current and dielectric constant were decreased. The thicker the layer deposited at room temperature was, the lower dielectric constant was. However, leakage current was indepenent of the variation of the thickness ratio. The sample with 200$\AA$ of the layer deposited at room temperature showed the most promising results in both dielectric constant and leakage current.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 C
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• pp.1476-1478
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• 2002

In recent years, the tantalum nitride(TaN) thin-film has been developed for the electronic resistor, inductor and capacitor. In this papers, this study presents the surface profile and sheet-resistance property relationship of reactive-sputtered TaN thin film resistor processed by TaN(tantalum nitride) on alumina substrate. The TCR properties of the TaN films were discussed in terms of crystallization and thin films surface morphology due to annealing temperature. It is clear that the TaN thin-films resistor electrical properties are low TCR related with it's annealing temperature and ambient annealing condition. Respectively, at $300{\sim}400^{\circ}C$ on vacuum and nitrogen annealed thin film resistor having a goof thermal stability and lower TCR properties then as deposited thin films expected for the application to the dielectric material of passive component.

• 대한전자공학회논문지SD
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• 제38권5호
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• pp.329-337
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• 2001

고유전 (Ba, Sr)TiO/sub 3/ (BST) 박막을 이용한 DRAM storage capacitor의 저전계 영역에서의 전하손실을 발생시키는 커패시터의 누설전류는 유전완화전류와 진성 누설전류로 이루진다고 알려져 있다. 특히, 기가급 DRAM의 동작 전압(~IV)에서 유전완화전류가 진성 누설전류에 비해 훨씬 크기 때문에 이에 대한 심도 있는 연구가 필요하다. 본 연구에서는 thermally stimulated current (TSC) 측정법을 BST 박막에 처음으로 적용하여 트랩의 에너지 level 및 공정변화에 따른 트랩 밀도의 상대적 평가를 하였다. 그리고, 기존에 사용되던 전류-전압(I-V) 측정이나 전류-시간(I-t) 측정과 비교 및 분석함으로써 유전완화 전류의 원인을 규명하고 TSC 측정법의 신뢰성을 살펴보았다. 먼저 안정적인 TSC 측정을 위해 전계, 시간, 온도 및 승온속도에 따른 polarization condition을 알아보았다 이 조건을 이용한 TSC 측정으로부터 BST 박막에서의 트랩의 energy level이 0.20(±0.01) eV와 0.45(±0.02) eV임을 알 수 있었다. Rapid thermal annealing (RTA)을 이용한 후속 열처리에 따른 TSC 측정을 통하여 이 트랩들이 산소결핍(oxygen vacancy)에 기인함을 확인할 수 있었다. MIM BST 커패시터의 열처리에 대한 TSC 특성은 전류-전압(I-V) 및 전류-시간(I-t) 특성과 같은 경향성을 보인다. 이것은 TSC 측정이 BST 박막내의 트랩을 평가하는데 있어서 매우 효과적인 방법이라는 것을 보여준다.