• 제목/요약/키워드: dielectric mask

검색결과 35건 처리시간 0.027초

유연한 기판상의 유기 트랜지스터의 절연 표면층 상태 변화에 의한 전기적 특성 향상 (Changes of dielectric surface state In organic TFTs on flexible substrate)

  • 김종무;이주원;김영민;박정수;김재경;장진;오명환;주병권
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 춘계학술대회 논문집 디스플레이 광소자분야
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    • pp.86-89
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    • 2004
  • Organic thin film transistors (OTFTs) are fabricated on the plastic substrate through 4-level mask process without photolithographic patterning to yield the simple fabrication process. And we herewith report for the effect of dielectric surface modification on the electrical characteristics of OTFTs. The KIST-JM-1 as an organic molecule for the surface modification is deposited onto the surface of zirconium oxide $(ZrO_2)$ gate dielectric layer. In this work, we have examined the dependence of electrical performance on the interface surface state of gate dielectric/pentacene, which may be modified by chemical properties in the gate dielectric surface.

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Vapor Deposition Polymerization 방법을 이용한 유기 박막 트렌지스터의 제작 (Fabrication of Organic Thin-Film Transistor Using Vapor Deposition Polymerization Method)

  • 표상우;김준호;김정수;심재훈;김영관
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 하계학술대회 논문집
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    • pp.190-193
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    • 2002
  • The processing technology of organic thin-film transistors (Ons) performances have improved fur the last decade. Gate insulator layer has generally used inorganic layer, such as silicon oxide which has properties of a low electrical conductivity and a high breakdown field. However, inorganic insulating layers, which are formed at high temperature, may affect other layers termed on a substrate through preceding processes. On the other hand, organic insulating layers, which are formed at low temperature, dose not affect pre-process. Known wet-processing methods for fabricating organic insulating layers include a spin coating, dipping and Langmuir-Blodgett film processes. In this paper, we propose the new dry-processing method of organic gate dielectric film in field-effect transistors. Vapor deposition polymerization (VDP) that is mainly used to the conducting polymers is introduced to form the gate dielectric. This method is appropriate to mass production in various end-user applications, for example, flat panel displays, because it has the advantages of shadow mask patterning and in-situ dry process with flexible low-cost large area displays. Also we fabricated four by four active pixels with all-organic thin-film transistors and phosphorescent organic light emitting devices.

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$O_2/CF_4$ 유도결합 플라즈마를 이용한 Polyimide 박막의 식각 특성 (Etching Characteristics of Polyimide Film as Interlayer Dielectric Using Inductively Coupled ($O_2/CF_4$)Plasma)

  • 강필승;김창일
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2001년도 하계학술대회 논문집 C
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    • pp.1509-1511
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    • 2001
  • In this study, etching characteristics of polyimide(Pl) film with $O_2/CF_4$ gas mixing ratio was studied using inductively coupled plasma (ICP). The etch rate and selectivity were evaluated to chamber pressure and gas mixing ratio. High etch rate (over 8000$\AA$/min) and vertical profile were acquired in $CF_4$/($CF_4+O_2$) of 0.2. The selectivities of polyimide to PR and polyimide to $SiO_2$ were 1.15, 5.85, respectively. The profiles of polyimide film etched in $CF_4/O_2$ were measured by a scanning electron microscope (SEM) with using an aluminum hard mask pattern. The chemical states on the polyimide film surface were measured by x-ray photoelectron spectroscopy (XPS).

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신경신호기록용 탐침형 반도체 미세전극 어레이의 제작 (Fabrication of Depth-probe type Silicon Microelectrode array for Neural signal Recording)

  • 윤태환;황은정;신동용;김성준
    • 대한의용생체공학회:학술대회논문집
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    • 대한의용생체공학회 1998년도 추계학술대회
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    • pp.147-148
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    • 1998
  • In this paper, we developed the process for depth-probe type silicon microelectrode arrays. The process consists of four mask steps only. The steps are for defining sites, windows, and for shaping probe using plasma etch from above, and for shaping using wet etch from below, respectively. The probe thickness is controlled by dry etching, not by impurity diffusion. We used gold electrodes with a triple dielectric system consisting of oxide/nitride/oxide. The shank of the probe taper from 200um to tens of urn tip and has 30 um thickness.

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5GHz 무선랜 응용을 위한 소형 광대역 MEMS 안테나 (A Small Size Broadband MEMS Antenna for 5 GHz WLAN Applications)

  • 김지혁;김현철;전국진
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.603-604
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    • 2006
  • A small size broadband microstrip patch antenna with small ground plane has been fabricated using MEMS. Multiple layer of high and low dielectric substrates are used to realize small size and broadband characteristics. The microstrip patch is divided into 4 pieces and each patch is connected to each other using a metal microstrip line. The fabrication process is very simple and only one mask is needed. Two types of microtrip antennas are fabricated. Type A is the microstrip antenna with metal lines and type B is the microstrip antenna without metal lines. The size of proposed microstip antenna is $8*12*2mm^3$ and the experimental results show that the antenna type A and type B have the bandwidth of 420MHz at 5.3 GHz and 480MHz at 5.66 GHz, respectively.

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BTO 박막의 화학적 기계적 연마 특성 연구 (Study on Characteristics of Chemical Mechanical Polishing of BTO Thin Film)

  • 고필주;김남훈;박진성;서용진;이우선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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    • pp.113-114
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    • 2005
  • Sufficient removal rate with adequate selectivity to realize the pattern mask of tetra-ethyl ortho-silicate (TEOS) film for the vertical sidewall angle were obtained by chemical mechanical polishing (CMP) with commercial silica slurry as a function of pH variation. The changes of X-ray diffraction pattern and dielectric constant by CMP process were negligible.

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소자분리를 위한 선택적 실리콘 에피택시 (Selective Si Epitaxy for Device Isolation)

  • 양전욱;조경익;박신종
    • 대한전자공학회논문지
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    • 제23권6호
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    • pp.801-806
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    • 1986
  • The effect of SiH2Cl2 -HCl gas on the growth rate of epitaxial layer is studied. The temperature, pressure and gas mixing ratio of SiH2Cl2 and HCl are varied to study the growth rate dependence and selective Si epitaxy. The P-n junction diode is fabricated on the epitaxial layer and electrical characteristics are examined. Also, using selective Si epitaxy, a possibility of thin dielectric isolation process, that gives an independent isolation width on the mask dimension, is examined.

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Low-k Polyimide상의 금속배선 형성을 위한 식각 기술 연구 (A Study on the Etcting Technology for Metal Interconnection on Low-k Polyimide)

  • 문호성;김상훈;안진호
    • 한국재료학회지
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    • 제10권6호
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    • pp.450-455
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    • 2000
  • 실리콘 소자가 더욱 미세화되면서, 발생되는 power consumption, crosstalk와 interconnection delay 등을 감소시키기 위해 $SiO_2$ 대신에 저유전 상수막의 적용이 고려되어진다. 본 논문에서는, 저유전 상수 층간 절연막 재료로 유망한 폴리이미드의 식각 특성에 $O_2/SF_6$ 가스가 미치는 영향을 연구하였다. 폴리이미드의 식각률을 SF(sub)6 가스의 첨가에 따라 산소와 hydrocarbon 폴리머 간의 반응을 억제하는 비휘발성 물질은 fluorine 화합물의 형성에 의해 감소되었다. 반면에, 기판 전극의 전압 증가는 물리적인 충격을 통해 식각 공정을 증가시켰다. 또한 작은 량의 SF(sub)6 가스 첨가는 식각 topography에 바람직하였다. 폴리이미드 식각을 위한 $SiO_2$ hard mask 사용은 산소 플라즈마 식각 하에서 효과적이었다(선택비-30). 반면에 $O_2SF_6$ 가스 조성은 식각 선택비를 4로 저하시키게 되었다. 이러한 결과를 기초로, $1-2\mu\textrm{m}$ 선폭을 가진 PI 2610의 식각을 원활히 수행할 수 있었다.

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$BaTiO_3$$TiO_2$ 연마제 첨가를 통한 BTO박막의 CMP (CMP of BTO Thin Films using $TiO_2$ and $BaTiO_3$ Mixed Abrasive slurry)

  • 서용진;고필주;김남훈;이우선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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    • pp.68-69
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    • 2005
  • BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant. It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the self-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS), respectively. The removal rate of BTO thin film using the$ BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%. The sufficient within-wafer non-uniformity (WIWNU%)below 5% was obtained in each abrasive at all concentrations. The surface morphology of polished BTO thin film was investigated by atomic force microscopy (AFM).

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연마제 첨가를 통한 BTO Film의 CMP (CMP of BTO Thin Films using Mixed Abrasive slurry)

  • 김병인;이기상;박정기;정창수;강용철;차인수;정판검;신성헌;고필주;이우선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 영호남 합동 학술대회 및 춘계학술대회 논문집 센서 박막 기술교육
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    • pp.101-102
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    • 2006
  • BTO ($BaTiO_3$) thin film is one of the high dielectric materials for high-density dynamic random access memories (DRAMs) due to its relatively high dielectric constant, It is generally known that BTO film is difficult to be etched by plasma etching, but high etch rate with good selectivity to pattern mask was required. The problem of sidewall angle also still remained to be solved in plasma etching of BTO thin film. In this study, we first examined the patterning possibility of BTO film by chemical mechanical polishing (CMP) process instead of plasma etching. The sputtered BTO film on TEOS film as a stopper layer was polished by CMP process with the sell-developed $BaTiO_3$- and $TiO_2$-mixed abrasives slurries (MAS). respectively. The removal rate of BTO thin film using the $BaTiO_3$-mixed abrasive slurry ($BaTiO_3$-MAS) was higher than that using the $TiO_2$-mixed abrasive slurry ($TiO_2$-MAS) in the same concentrations. The maximum removal rate of BTO thin film was 848 nm/min with an addition of $BaTiO_3$ abrasive at the concentration of 3 wt%.

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