• Journal of the Microelectronics and Packaging Society
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• v.17 no.2
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• pp.55-61
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• 2010

The device with tantalum silicide heater were bonded by Ag paste and Au SBB(Stud Bump Bonding) onto the Au coated substrate. The shear test after Au ABB and the thermal performance under current stressing were measured. The optimum condition of Au SBB was determined by fractured surface after die shear test and $350^{\circ}C$ for substrate, $250^{\circ}C$ for die during flip chip bonding with bonding load of about 300 g/bump. With applying 5W through heater on the device, the maximum temperature with Ag paste bonding was about $50^{\circ}C$. That with Au SBB on Au coated Si substrate showed $64^{\circ}C$. The difference of maximum temperatures is only $14^{\circ}C$, even though the difference of contact area between Ag paste bonding and Au SBB is by about 300 times and the simulation showed that the contact resistance might be one of the reasons.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.8
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• pp.3301-3306
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• 2012

In LED chip packaging, die bonding is a very important process which fixes the LED chip on the lead frame to provide enough strength for the next process. Conventional pick-up device of the die bonder is simply operated by up and down motion of a collet and an ejector pin. However, this method may cause undesired problems such as position misalignment and/or severe die damage when the pick-up device reaches the die. In this study, to minimize the position alignment error and die damage, a die bonder is developed by adopting a new pick-up head for precise alignment and high speed feeding. To evaluate structural stability of the designed system, required finite element model of the die bonder is generated, and structural analysis is performed. Vibration analysis of the pick-up head is also performed using developed finite element model at operation frequency range. As a result of the analysis, deformation, stress, and natural frequency of the die bonder are investigated.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• ETRI Journal
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• v.34 no.3
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• pp.388-398
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• 2012

Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multilayer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.6
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• pp.166-173
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• 2001

Composite materials consists of two or more different material layers. The usefulness of clad metal rods forms the possibilities of combination of properties of different metals. Copper clad aluminum composite materials are being used for economic and structural purpose. In this study, composite billet consists of commercially pure copper and aluminum(A6061) and experimental conditions consist of the combinations of clad thickness, extrusion ratio, and semi-cone angle of die. In order to investigate the influence of these parameters on the hot direct extrudability of the copper clad aluminum composite material rods, the experimental study have been performed with various extrusion temperatures, extrusion ratios, semi-cone angles of die, and composition rate of Cu:Al.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1832-1835
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• 2003

This paper suggests the selective ultra precision polishing techniques for micro die and mold parts using magnetic-assisted machining. Fabrication of magnetic abrasive particle and their polishing performance are key technology at ultra precision polishing process of micro parts. Conventional magnetic abrasives have disadvantages. which are missing of abrasive particle and inequality between magnetic particle and abrasive particle. So, bonded magnetic abrasive particles are fabricated by several method. For example, plasma melting and direct bonding. Ferrite and carbonyl iron powder are used as magnetic particle where silicon carbide and Al$_2$O$_3$ are abrasive particle. Developed particles are analyzed using measurement device such as SEM. Possibility of magnetic abrasive and polishing performance of this magnetic abrasive particles also have been investigated. After polishing, surface roughness of workpiece is reduced from 2.927 $\mu\textrm{m}$ Rmax to 0.453 $\mu\textrm{m}$ Rmax.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.69-77
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• 2016

We propose nano-scale Cu direct bonding technology using ultra-high density Cu nano-pillar (CNP) with for high stacking yield exascale 2.5D/3D integration. We clarified the joining mechanism of nano-scale Cu direct bonding using CNP. Nano-scale Cu pillar easily bond with Cu electrode by re-crystallization of CNP due to the solid phase diffusion and by morphology change of CNP to minimize interfacial energy at relatively lower temperature and pressure compared to conventional micro-scale Cu direct bonding. We confirmed for the first time that 4.3 million electrodes per die are successfully connected in series with the joining yield of 100%. The joining resistance of CNP bundle with $80{\mu}m$ height is around 30 m for each pair of $10{\mu}m$ dia. electrode. Capacitance value of CNP bundle with $3{\mu}m$ length and $80{\mu}m$ height is around 0.6fF. Eye-diagram pattern shows no degradation even at 10Gbps data rate after the lamination of anisotropic conductive film.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.3
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• pp.649-657
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• 2008

This paper describes the optimized output performances such as output power and the third order intermodulation in GaN high power transistor packages which consist of chip die, chip capacitors, and wire bonding. The optimized output power according to wire bonding techniques, and third order intermodulation performances according to wire bonding and bias conditions are discussed. In addition, it is shown through the nonlinear simulation that how the output performances are sensitive to the inductance values which are realized by wire bonding for matching network in the limited package area.