• Title/Summary/Keyword: device simulations

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Molecular Dynamics Simulations of Nanomemory Element Based on Boron Nitride Nanotube-to-peapod Transition

  • Hwang Ho Jung;Kang Jeong Won;Byun Ki Ryang
    • Transactions on Electrical and Electronic Materials
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    • v.5 no.6
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    • pp.227-232
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    • 2004
  • We investigated a nonvolatile nanomemory element based on boron nitride nanopeapods using molecular dynamics simulations. The studied system was composed of two boron-nitride nanotubes filled Cu electrodes and fully ionized endo-fullerenes. The two boron-nitride nanotubes were placed face to face and the endo-fullerenes came and went between the two boron-nitride nanotubes under alternatively applied force fields. Since the endo-fullerenes encapsulated in the boron-nitride nanotubes hardly escape from the boron-nitride nanotubes, the studied system can be considered to be a nonvolatile memory device. The minimum potential energies of the memory element were found near the fullerenes attached copper electrodes and the activation energy barrier was $3{\cdot}579 eV$. Several switching processes were investigated for external force fields using molecular dynamics simulations. The bit flips were achieved from the external force field of above $3.579 eV/{\AA}$.

Electrostatic Discharge Analysis of n-MOSFET (n-MOSFET 정전기 방전 분석)

  • 차영호;권태하;최혁환
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.8
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    • pp.587-595
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    • 1998
  • Transient thermal analysis simulations are carried out using a modeling program to understand the human body model HBM ESD. The devices were simulated a one-dimensional device subjected to ESD stress by solving Poison's equation, the continuity equation, and heat flow equation. A ramp rise with peak ESD voltage during rise time is applied to the device under test and then discharged exponentially through the device. LDD and NMOS structures were studied to evaluate ESD performance, snap back voltages, device heating. Junction heating results in the necessity for increased electron concentration in the space charge region to carry the current by the ESD HBM circuit. The doping profile adihacent to junction determines the amount of charge density and magnitude of the electric field, potential drop, and device heating. Shallow slopes of LDD tend to collect the negative charge and higher potential drops and device heating.

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Fast Device Discovery for Remote Device Management in Lighting Control Networks

  • Choi, Sang-Il;Lee, Sanghun;Koh, Seok-Joo;Lim, Sang-Kyu;Kim, Insu;Kang, Tae-Gyu
    • Journal of Information Processing Systems
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    • v.11 no.1
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    • pp.125-133
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    • 2015
  • The Remote Device Management (RDM) protocol is used to manage the devices in the lighting control networks. RDM provides bi-directional communications between a controller and many lighting devices over the DMX512-A network. In RDM, using a simple binary search scheme, which is based on the 48-bit unique ID (UID) of each device, discovers the lighting devices. However, the existing binary search scheme tends to require a large delay in the device discovery process. In this paper, we propose a novel partition-based discovery scheme for fast device discovery in RDM. In the proposed scheme, all devices are divided into several partitions as per the device UID, and the controller performs device discovery for each partition by configuring a response timer that each device will use. From numerical simulations, we can see that there is an optimal number of partitions to minimize the device discovery time for a given number of devices in the proposed scheme, and also that the proposed partition-based scheme can reduce the device discovery time, as compared to the existing binary search scheme.

A new p-i-n/HBT photoreceiver design procedure for the optimum sensitivity (최적의 감도를 얻을 수 있는 p-i-n/HBT OEIC 광수신단의 새로운 설계방법)

  • ;;;M.B.Das
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.11
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    • pp.79-85
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    • 1995
  • In this paper, an epi layer and a device structure for InP/InGaAs p-i-n/HBT OEIC is designed for a receiving frontend of high speed optical communications. A 3 stage transimpedance circuit using the p-i-n/HBT device is also designed by SPICE simulations for a high sensitivity including ISI noises at a given bit rate. Our simulations show that the Personick's assumption which is not commonly satisfied have estimated a photoreceiver sensitivity too high, so thus we have to also consider ISI noises in OCIC receiver designs.

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Characterization of Channel Electric Field in LDD MOSFET (LDD MOSFET 채널 전계의 특성해석)

  • Park, Min-Hyoung;Han, Min-Koo
    • Proceedings of the KIEE Conference
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    • 1988.11a
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    • pp.363-367
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    • 1988
  • A simple analytical model for the lateral channel electric field in gate - offset structured Lightly Doped Drain MOSFET has been developed. The model's results agree well with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field as function of drain and gate bias conditions and process, design parameters. Advantages of analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate / drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot - electron phenomena, individually. We are able to find the optimum doping concentration of LDD minimizing the peak electric field and hot - electron effects.

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Impact of Fin Aspect Ratio on Short-Channel Control and Drivability of Multiple-Gate SOI MOSFET's

  • Omura, Yasuhisa;Konishi, Hideki;Yoshimoto, Kazuhisa
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.4
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    • pp.302-310
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    • 2008
  • This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio ($R_{h/w}$) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing MuGFET's. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guideline of w < L/3, where L is the channel length, is essential to suppress the short-channel effects of TG-FET.

Effects on Vehicle Handling Performance according to Camber Angle Change of Front and Rear Wheel (전륜 및 후륜 캠버각 변화에 따른 차량 조종성능 효과 분석)

  • Park, Seong-Jun;Sohn, Jeong-Hyun
    • Transactions of the Korean Society of Automotive Engineers
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    • v.19 no.6
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    • pp.23-29
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    • 2011
  • In this study, a camber angle generating mechanism for front and rear suspension is suggested. An experimental device is implemented and tested. A full vehicle model with camber angle generating device by using ADAMS/Car is modeled. Step steer simulations are carried out for investigating the effects of vehicle handling performance due to camber angle change of front and rear wheel. According to results, the camber angle of rear suspension affects the vehicle handling performance during both simulations. Therefore, when the vehicle makes the right turn or left turn, left and right wheel of front and rear suspension should have the proper orientation for improving the handling performance, respectively.

Characterization of Channel Electric Field in LDD MOSFET (LDD MOSFET채널 전계의 특성 해석)

  • 한민구;박민형
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.38 no.6
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    • pp.401-415
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    • 1989
  • A simple but accurate analytical model for the lateral channel electric field in gate-offset structured Lightly Doped Drain MOSFET has been developed. Our model assumes Gaussian doping profile, rather than simple uniform doping, for the lightly doped region and our model can be applied to LDD structures where the junction depth of LDD is not identical to the heavily doped drain. The validity of our model has been proved by comparing our analytical results with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field on the drain and gate bias conditions and process, design parameters. Advantages of our analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate/drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot-electron pohenomena, individually. Our model can also find the optimum doping concentration of LDD which minimizes the peak electric field and hot-electron effects.

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Location-Based Device Identification Algorithm for Device-to-Device Communication (기기간 직접통신을 위한 위치 정보 기반의 기기 식별 방법)

  • Park, Eunhye;Kang, Joonhyuk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38A no.10
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    • pp.893-897
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    • 2013
  • Recently the interest on device-to-device (D2D) communication has been increased due to the growing popularization of smart phones and tablet PCs. However, existing device identification mechanisms of D2D communication provide a text-based long list of possible devices, which leads the users to avoid to use D2D techniques. In this paper, we propose a location-based device identification technique for D2D communication. This paper describes the algorithm, analyzes its accuracy using analytical models, and verifies the results using computer simulations. The proposed algorithm is more user-friendly and intuitive way than existing D2D techniques.

Influence of geometry and loading conditions on the dynamics of martensitic fronts

  • Berezovski, Arkadi
    • Smart Structures and Systems
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    • v.4 no.2
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    • pp.123-135
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    • 2008
  • Damping capacity of SMA damping devices is simulated numerically under distinct geometry and loading conditions. Two-dimensional numerical simulations are performed on the basis of a phenomenological model of dynamics of martensite-austenite phase boundaries. Results of the simulations predict the time delay and the value of the stress transferred to other parts of a construction by a damper device.