• 대한전자공학회논문지SD
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• 제45권5호
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• pp.1-11
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• 2008

본 논문에서는 디지털 코드 오차 보정 기법을 사용한 15비트 50MS/s CMOS 파이프라인 ADC를 제안한다. 제안하는 ADC는 15비트 수준의 고해상도에서 면적과 전력 소모를 최소화하기 위해서 4단 파이프라인 구조를 사용하며 전체 ADC의 아날로그 회로를 변경하지 않고 첫 번째 단에 약간의 디지털 회로만을 추가하는 디지털 코드 오차 보정 기법을 적용한다. 첫 번째 단에서 소자 부정합으로 인해 발생하는 코드 오차는 나머지 세 단에 의해 측정된 후 메모리에 저장되고 정상 동작 시 메모리에 저장된 코드 오차를 디지털 영역에서 제거하여 보정한다. 모든 MDAC 커패시터 열에는 주변 신호에 덜 민감한 3차원 완전 대칭 구조의 레이아웃 기법을 적용하여 소자 부정합에 의한 영향을 최소화하면서 동시에 첫 번째 단의 소자 부정합을 보다 정밀하게 측정하도록 하였다. 시제품 ADC는 0.18um CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 15비트 해상도에서 각각 0.78LSB 및 3.28LSB의 수준을 보이며, 50MS/s의 샘플링 속도에서 최대 SNDR 및 SFDR은 각각 67.2dB 및 79.5dB를 보여준다. 시제품 ADC의 칩 면적은 $4.2mm^2$이며 전력 소모는 2.5V 전원 전압에서 225mW이다.

• 한국광학회지
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• 제18권1호
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• pp.1-7
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• 2007

필터와 검출기로 구성된 필터식 색채계의 분광감응도는 국제조명위원회(Commission Internationale de I'Eclairage, CIE)에서 정의한 등색함수와 일치해야 한다. 본 연구에서는 정확도가 높은 색채계에 적용할 수 있는 등색함수 $\bar{x},\;\bar{y}\;\bar{z}$에 대한 필터를 상용화된 색필터를 조합하여 제작할 수 있도록 설계하였다. 특히 등색함수 $\bar{x}$는 두 개의 투과대역을 가지고 있기 때문에 파장 영역이 다른 2 개의 필터로 분리하여 실현하였다. 설계에는 색필터의 두께를 곡선 맞춤변수로 두고 비선형 최소제곱법으로 필터의 품질지수 $f{_1}'$ 값을 최적화하는 프로그램을 개발하여 사용하였다. 그 결과 모든 필터의 $f{_1}'$ 값이 3 % 이하가 되도록 설계할 수 있었으며, $\bar{y}$ 등색함수 필터를 실제로 제작하여 $f{_1}'$ 측정값이 2.8 %임을 검증하였다. 또한 설계한 등색함수 필터로 색채계를 제작하여 LCD 평판 디스플레이의 색채 측정에 사용할 경우 발생하는 계통오차도 산출하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.50-50
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• 2008

ZnO has been extensively studied for optoelectronic applications such as blue and ultraviolet (UV) light emitters and detectors, because it has a wide band gap (3.37 eV) anda large exciton binding energy of ~60 meV over GaN (~26 meV). However, the fabrication of the light emitting devices using ZnO homojunctions is suffered from the lack of reproducibility of the p-type ZnO with high hall concentration and mobility. Thus, the ZnO-based p-n heterojunction light emitting diode (LED) using p-Si and p-GaN would be expected to exhibit stable device performance compared to the homojunction LED. The n-ZnO/p-GaN heterostructure is a good candidate for ZnO-based heterojunction LEDs because of their similar physical properties and the reproducibleavailability of p-type GaN. Especially, the reduced lattice mismatch (~1.8 %) and similar crystal structure result in the advantage of acquiring high performance LED devices with low defect density. However, the electroluminescence (EL) of the device using n-ZnO/p-GaN heterojunctions shows the blue and greenish emissions, which are attributed to the emission from the p-GaN and deep-level defects. In this work, the n-ZnO:Ga/p-GaN:Mg heterojunction light emitting diodes (LEDs) were fabricated at different growth temperatures and carrier concentrations in the n-type region. The effects of the growth temperature and carrier concentration on the electrical and emission properties were investigated. The I-V and the EL results showed that the device performance of the heterostructure LEDs, such as turn-on voltage and true ultraviolet emission, developed through the insertion of a thin intrinsic layer between n-ZnO:Ga and p-GaN:Mg. This observation was attributed to a lowering of the energy barriers for the supply of electrons and holes into intrinsic ZnO, and recombination in the intrinsic ZnO with the absence of deep level emission.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Journal of Platform Technology
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• 제9권1호
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• pp.15-22
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• 2021

In a smart manufacturing environment, more and more devices are connected to the Internet so that a large volume of data can be obtained during all phases of the product life cycle. The large-scale industries, companies and organizations that have more operational units scattered among the various geographical locations face a huge resource consumption because of their unorganized structure of sharing resources among themselves that directly affects the supply chain of the corresponding concerns. Cloud-based smart manufacturing paradigm facilitates a new variety of applications and services to analyze a large volume of data and enable large-scale manufacturing collaboration. The manufacturing units include machinery that may be situated in different geological areas and process instances that are executed from different machinery data should be constantly managed by the super admin to coordinate the manufacturing process in the large-scale industries these environments make the manufacturing process a tedious work to maintain the efficiency of the production unit. The data from all these instances should be monitored to maintain the integrity of the manufacturing service system, all these data are computed in the cloud environment which leads to the latency in the performance of the smart manufacturing service system. Instead, validating data from the external device, we propose to validate the data at the front-end of each device. The validation process can be automated by script validation and then the processed data will be sent to the cloud processing and storing unit. Along with the end-device data validation we will implement the APM(Asset Performance Management) to enhance the productive functionality of the manufacturers. The manufacturing service system will be chunked into modules based on the functionalities of the machines and process instances corresponding to the time schedules of the respective machines. On breaking the whole system into chunks of modules and further divisions as required we can reduce the data loss or data mismatch due to the processing of data from the instances that may be down for maintenance or malfunction ties of the machinery. This will help the admin to trace the individual domains of the smart manufacturing service system that needs attention for error recovery among the various process instances from different machines that operate on the various conditions. This helps in reducing the latency, which in turn increases the efficiency of the whole system

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.235-235
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• 2009

This paper describes the influence of a polycrystalline (poly) 3C-SiC buffer layer on the surface acoustic wave (SAW) properties of poly aluminum nitride (AlN) thin films by comparing the center frequency, insertion loss, the electromechanical coupling coefficient ($k^2$), andthetemperaturecoefficientoffrequency(TCF) of an IDT/AlN/3C-SiC structure with those of an IDT/AlN/Si structure, The poly-AlN thin films with an (0002)-preferred orientation were deposited on a silicon (Si) substrate using a pulsed reactive magnetron sputtering system. Results show that the insertion loss (21.92 dB) and TCF (-18 ppm/$^{\circ}C$) of the IDT/AlN/3C-SiC structure were improved by a closely matched coefficient of thermal expansion (CTE) and small lattice mismatch (1 %) between the AlN and 3C-SiC. However, a drawback is that the $k^2(0.79%)$ and SAW velocity(5020m/s) of the AlN/3C-SiC SAW device were reduced by appearing in some non-(0002)AlN planes such as the (10 $\bar{1}$ 2) and (10 $\bar{1}$ 3) AlN planes in the AlN/SiC film. Although disadvantages were shown to exist, the use of the AlN/3C-SiC structure for SAW applications at high temperatures is possible. The characteristics of the AlN thin films were also evaluated using FT-IR spectra, XRD, and AFM images.

• 대한한의진단학회지
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• 제11권1호
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• pp.48-60
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• 2007

Palpation of the pulse has been used in Korean traditional medicine since ancient times to assess physical health. Pulse wave contour may be obtained by measuring arterial pressure or blood volume change of skin. The latter is called as Photoplethysmography(PPG) or digital volume pulse(DVP). The PPG signal is measured by a device comprising an infrared light sourece and a photodetector. Although less widely used, this technique deserves further consideration because of its simplicity and ease of use. The contour of the PPG is formed as a result of a complex interaction between the left ventricle and the systemic circulation. It usually exhibits an early systolic peak and an early diastolic peak. the first peak is formed mainly by pressure trasmitted along a direct path from the left ventricle to the finger. The second peak is formed in part by pressure transmitted along the aorta and large arteries to sites of impedance mismatch in the lower body. The contour of the PPG is sensitive to changes in arterial tone and is influenced by ageing and large artery stiffness. Measurements taken directly from the PPG or from its second derivative can be used to assess these properties. In some mathematical approaches, the extraction of periodic components using frequency analysis was tried to analysis of the PPG. But we don't understand yet what kind of factor in the cardiovascular system or human body is related with the respective specific Fourier components of PPG. This review describes the background to measurement principles, representative contour, contour analysis and frequency domain analysis of PPG, and current and future.

• Journal of electromagnetic engineering and science
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• 제18권3호
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• pp.188-198
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• 2018

In this study, we propose an approach for the design and satisfy the requirements of the fabrication of a small, lightweight, reliable, and stable ultra-wideband receiver for millimeter-wave bands and the contents of the approach. In this paper, we designed and fabricated a stable receiver with having low noise figure, flat gain characteristics, and low noise characteristics, suitable for millimeter-wave bands. The method uses the chip-and-wire process for the assembly and operation of a bare MMIC device. In order to compensate for the mismatch between the components used in the receiver, an amplifier, mixer, multiplier, and filter suitable for wideband frequency characteristics were designed and applied to the receiver. To improve the low frequency and narrow bandwidth of existing products, mathematical modeling of the wideband receiver was performed and based on this spurious signals generated from complex local oscillation signals were designed so as not to affect the RF path. In the ultra-wideband receiver, the gain was between 22.2 dB and 28.5 dB at Band A (input frequency, 18-26 GHz) with a flatness of approximately 6.3 dB, while the gain was between 21.9 dB and 26.0 dB at Band B (input frequency, 26-40 GHz) with a flatness of approximately 4.1 dB. The measured value of the noise figure at Band A was 7.92 dB and the maximum value of noise figure, measured at Band B was 8.58 dB. The leakage signal of the local oscillator (LO) was -97.3 dBm and -90 dBm at the 33 GHz and 44 GHz path, respectively. Measurement was made at the 15 GHz IF output of band A (LO, 33 GHz) and the suppression characteristic obtained through the measurement was approximately 30 dBc.

• 전자공학회논문지
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• 제50권10호
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• pp.91-97
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• 2013

본 논문에서는 NTSC/PAL 아날로그 TV를 구동하기 위한 10-bit current steering D/A 변환기를 제안하였다. 제안하는 D/A 변환기는 50MS/s 의 동작속도를 가지며, 6+4 분할 구조로 설계되었다. 또한 새로운 개념의 자가보정 바이어스 기법을 적용하여 칩 내부의 종단저항을 사용하고도 공정오차를 최소화 하였다. 제안하는 D/A 변환기는 3.3V 0.11um 1-poly 6-metal CMOS 공정을 사용하여 제작되었다. 제작된 칩의 유효 면적은 $0.35mm^2$, 3.3V 전원전압 상에서 약 88mW의 전력소모를 나타내었다. 실험 결과는 변환 속도 50MS/s, 입력 주파수 1MHz에서 SFDR 63.1dB의 특성을 나타내었다.

• 마이크로전자및패키징학회지
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• 제11권4호
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• pp.13-22
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• 2004

MEMS 소자의 패키지는 일반적으로 패키징 과정에서 큰 온도변화를 받게 되는데, 이에 의한 패키지의 변형은 패키지 및 소자의 신뢰성에 큰 영향을 미칠 수 있다. 본 논문에서는 진동형 MEMS 자이로스코프 센서의 패키지를 대상으로 하여, 온도변화로 인한 열변형 거동에 대한 광학실험과 해석을 수행하였다. 이를 위하여 실시간 모아레 간섭계를 이용하여 각 온도단계에서 변위분포를 나타내는 간섭무늬를 얻고, 그로부터 MEMS 패키지의 굽힘변형 거동 및 인장변형에 대한 해석을 수행하였다. MEMS 칩과 EMC 및 PCB의 열팽창계수 차이로 인하여 패키지는 $125^{\circ}C$ 이하에서는 전체적으로 아래로 볼록한 굽힘변형이 발생하였으며, 온도 $140^{\circ}C$를 정점으로 그 이상의 온도에서는 반대의 굽힘변형이 발생하였다. MEMS의 주파수에 영향을 줄 수 있는 칩 자체의 수축변형률은 약 $481{\times}10^{-6}$로 측정되어서 MEMS 설계시 이를 고려하여야 함을 알 수 있다.