• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.212-221
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• 1996

A CMOS comparator is designed for low voltage and low power operations. The proposed comparator consists of a preadmplifier followed by a regenerative latch. The preasmplifier reduces the power consumption to a half with the power-down mode and the dynamic offsets of the latch, which is affected by each device mismatch, is statistically analyzed. The circuit is designed and simulated using a 0.8.mu.m n-well CMOS process and the dissipated power is 0.16mW at a 20MHz clock speed based on a 3V supply.

• Proceedings of the Korean Printing Society Conference
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• 2000.12a
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• pp.0.2-0
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• 2000

Most important step for the color matching in scanner is the color coordinate transformation from the scanner RGB space to device independent uniform color space. A variety of color calibration technologies have been developed for input device. Linear or nonlinear matrices have been conveniently applied to correct the color filter\`s mismatch with color matching function in scanners. The color matching accuracy is expected to be further improved when the nonlinear matrices are optimized into subdivided smaller color spaces than in single matrix of the entire color space. This article proposed the scanner calibration method using subspace division regression analysis and it were compared with conventional method.

• Journal of the Korean Graphic Arts Communication Society
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• v.19 no.1
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• pp.4-16
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• 2001

Most important step for the color matching in scanner is the color coordinate transformation from the scanner RGB space to device independent uniform color space. A variety of color calibration technologies have been developed for input device. Linear or nonlinear matrices have been conveniently applied to correct the color filter's mismatch with color matching function in scanners. The color matching accuracy is expected to be further improved when the nonlinear matrices are optimized into subdivided smaller color spaces than in single matrix of the entire color space. This article proposed the scanner calibration method using subspace division regression analysis and it were compared with conventional method.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.98-106
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• 1994

To realize high accuracy and high speed we developed a new self compensation scheme and applied it to a 10-bit D/A converter. This circuit can compensate the device mismatch without interrupting the D/A converter operation. With the compensation circuit,INA decreased down to 0.22LSB from 0.47LSB. The device was fabricated using a 0.8$\mu$m CMOS process. The area of the D/A converter core is 3.2mm$^{2}$ and the area of the compensation part is 0.64mm$^{2}$.

• Applied Science and Convergence Technology
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• v.23 no.3
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• pp.128-133
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• 2014

We study the ballistic spin transport properties in a two-dimensional electron gas system in the presence of magnetic barriers using a transfer matrix method. We concentrate on the size-effect of the magnetic barriers parallel to a two-dimensional electron gas plane. We calculate the transmission probability of the ballistic spin transport in the magnetic barrier structure while varying the width of the magnetic barriers. It is shown that resonant tunneling oscillation is affected by the width and height of the magnetic barriers sensitively as well as by the inter-spacing of the barriers. We also consider the effect of additional electrostatic modulation on the top of the magnetic barriers, which could enhance the current spin polarization. Because all-semiconductor-based devices are free from the resistance mismatch problem, a resonant tunneling structure using the two-dimensional electron gas system with electric-magnetic modulation would play an important role in future spintronics applications. From the results here, we provide information on the physical parameters of a device to produce well-defined spin-polarized current.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.580-587
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• 2003

In this paper, we introduce a novel model to analyze the linearity of a TW-EAM (traveling-wave electroabsorption modulator). The device length, microwave loss (ML), and internal reflection (IR) due to impedance mismatch have effect on the linearity of a TW-EAM. The longer devices have characteristics of lower biases with minimum IMDS (intermodulation distortions). ML decreases the output power as well as the IMD value. Internal reflection has different nonlinear characteristics according to the wavelength of the input frequency and the device length. There is little change in SFDR (spurious-free dynamic range) due to ML or IR. As a result, for a 50 GHz band RF-optical communication system, a 0.8 mm-long TW-EAM with the lowest ML would have better properties by using n, which is caused by impedance, mismatch at the output port.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.7
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• pp.491-499
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• 2018

The conventional calibration method for a noise figure analyzer is to use a noise source. This method is accompanied by a significant irregular ripple in the measurement results, because it does not consider the mismatch of the noise source and noise figure analyzer during calibration. A novel calibration method of the noise figure analyzer is proposed that considers the mismatch between the noise power and noise figure analyzer. A novel noise correlation matrix measurement technique using this method is also proposed. The method determines the noise correlation matrix and the gain of the uncorrected noise figure analyzer using uncorrected noise powers. Then, having determined the gain and noise correlation matrix, the effects of noise figure analyzers were corrected in the measurement results of the noise correlation matrix for the device under test (DUT). Through the proposed method, the measured noise parameters of a DUT showed the same degree of irregular ripples as the result of using the relative noise ratio.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.239-242
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• 1998

Ca $F_2$ films have superior gate insulator properties than conventional gate insulator such as $SiO_2$, Si $N_{x}$, $SiO_{x}$, and T $a_2$ $O_{5}$ to the side of lattice mismatch between Si substrate and interface trap charge density( $D_{it}$). Therefore, this material is enable to apply Thin Film Transistor(TFT) gate insulator. Most of gate oxide film have exhibited problems on high trap charge density, interface state in corporation with O-H bond created by mobile hydrogen and oxygen atom. This paper performed Ca $F_2$ property evaluation as MIM, MIS device fabrication. Ca $F_2$ films were deposited at the various substrate temperature using a thermal evaporation. Ca $F_2$ films was grown as polycrystalline film and showed grain size variation as a function of substrate temperature and RTA post-annealing treatment. C-V, I-V results exhibit almost low $D_{it}$(1.8$\times$10$^{11}$ $cm^{-1}$ /le $V^{-1}$ ) and higher $E_{br}$ (>0.87MV/cm) than reported that formerly. Structural analysis indicate that low $D_{it}$ and high $E_{br}$ were caused by low lattice mismatch(6%) and crystal growth direction. Ca $F_2$ as a gate insulator of TFT are presented in this paper paperaper

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.924-930
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• 1998

In this study, we describe the properties of an electro-optical modulator with CPW(coplanar waveguide) electrode fabricated on $LiNvO_3$ optical waveguide, that is applicable to optical communications. These optical modulators have features that use a buffer layer to reduce velocity mismatch between microwaves and optical wave as well as employ CPW to improve impedance and propagation mode mismatch between the electrode and the external circuits. And an annealed proton exchange technique for obtaining low-loss optical waveguides and good reproducibility was employed. Taking into consideration the mentioned background, to achieve the lower driving voltage of optical modulator, we have re-disigned the longer interaction length. And their device properties are discussed also. As a result, fabricated optical modulators of good 10Gps operation and low voltage(5.6V of the halfwave lengfth voltage) at an $1.5{\mu}m$ wavelength are achived with good reproducibility.