• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.303-317
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• 2013

Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.

• Journal of Astronomy and Space Sciences
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• v.31 no.3
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• pp.235-240
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• 2014

The communications link in a space program is a crucial point for upgrading its performance by handling data between spacecraft bus and payloads, because spacecraft's missions are related to the data handling mechanism using communications ports such as a controlled area network bus (CAN Bus) and a universal asynchronous receiver and transmitter (UART). The NEXTSat-1 has a lot of communications ports for performing science and technology missions. However, the top level system requirements for the NEXTSat-1 are mass and volume limitations. Normally, the communications for units shall be conducted by using point to point link which require more mass and volume to interconnect. Thus, our approach for the novel communications link in the NEXTSat-1 program is to use CAN and serializer and deserializer low voltage differential signal (SerDesLVDS) to meet the system requirements of mass and volume. The CAN Bus and SerDesLVDS were confirmed by using already defined communications link for our missions in the NEXTSat-1 program and the analysis results were reported in this study in view of data flow and size analysis.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1185-1188
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• 2003

This paper describes a design for a 2.5Gb/s serial data link CMOS transceiver based on the InfiniBand$^{TM}$ specification. The transceiver chip integrates data serializer, line driver, Tx PLL, deserializer, clock recovery, and lock detector. The designed transceiver is fabricated in a 0.25 ${\mu}{\textrm}{m}$ CMOS mixed-signal, 1-poly, 5-metal process. The first version chip occupies a 3.0mm x 3.3mm area and consumes 450mW with 2.5V supply. In 2.5 Gbps, the output jitter of transmitter measured at the point over a 1.2m, 50Ω coaxial cable is 8.811ps(rms), 68ps(p-p). In the receiver, VCO jitter is 18.5ps(rms), 130ps(p-p), the recovered data are found equivalent to the transmitted data as expected. In the design for second version chip, the proposed clock and data recovery circuit using linear phase detector can reduce jitter in the VCO of PLL.L.

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.67-72
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• 2015

For the development of UFS device test system, M-PHY specifications should be matched with MIPI-standard which is analog signal protocol. In this paper, the implementation methodology and hardware structure for the M-PHY AFE (Analog Front End) Block was suggested that it can be implemented using universal components without ASIC process. The testing procedure has a jitter problem so to solve the problems we using ASIC process, normally but the ASIC process needs a lot of developing cost making the UFS device test system. In is paper, the suggestion was verified by the output signal which was compared to the MIPI-standard on the Prototype-board using universal components. The board was reduced the jitter on the condition of HS-TX and 5.824 Gbps Mode in SerDes (Serialize-deserializer). Finally, the suggestion and developed AFE block have a useful better than ASIC process on developing costs of the industrial UFS device test system.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.154-158
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• 2005

In this paper, we design optical receiver composed of CDR(clock and data recovery), SA(sense amp), TIA(transimpe dence amplifier), and decision circuit. The optical receiver can be classified to two main block, one is Deserializer composed of CDR and SA, another is PD receiver composed of preamplifier(샴), peak detector, etc. In this paper, we propose CDR using delayed data topology that could improve defects of existing CDR. The optical receiver that is proposed in this paper has the role of translation a 1.25 Gb/s optical signal to $10{\times}125 Mb/s$ array electric signals. This optical receiver is verified by simulator(hspice) using 0.35 um CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.39-45
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• 2004

This paper describes the design and implementation of Serial ATA physical layer and performance measurement. It is composed of tranceiver circuit that has the NRZ data stream with +/-250㎷ voltage level and 1.5Gbps data rate, transmission PLL circuit, clock ＆ data recovery circuit, serializer/deserializer circuit and OOB(Out Of Band) generation/detection circuit. We implement the verification of the silicon chip with 0.18${\mu}{\textrm}{m}$ Standard CMOS process. It can be seen that all of the blocks operate with no errors but the data transfer rate is limited to the 1.28Gbps even this should support 1.5Gbps data transfer rate.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.149-156
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• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.167-174
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• 2012

The circuits including with Optical transceiver and clock data recovery, in this paper, SERDES (SERializer-DESerializer) are implemented to construct a GE-PON burst-mode transceiver supporting IEEE 802.3ah and a jig for measuring the burst-mode characteristics, that is to say, PON upstream optical transmission environment are manufactured to evaluate the performance of transceiver. we verified that the limiting amplifier compensated the gap of max. 26dB optical power by experiments. The startup acquisition lock time is 670ns in case of using VSC7123 and 2300ns in case of S2060 and the data acquisition lock time were measured to be 400ns and 600ns, respectively, in the upstream channel transmission in this work. While on the other, VSC7123 is satisfied with IEEE802.3ah recommendations.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.4 no.2
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• pp.29-36
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• 2005

All-optical fiber-type $2{\times}32$ splitters for an Ethernet PON (passive optical network) were fabricated by using a FBT (fiber biconical tapered) process and the performance of the splitters was tested in upstream transmission of the EPON system. The $2{\times}32$ splitters was obtained by cascading $1{\times}4$ splitters fabricated by a conventional FBT process and showed -18 dB of insertion loss with 1.5 dB uniformity of output power at each channel and -0.1 dB of polarization dependent loss. The insertion loss variation was below 0.1 dB at the temperature range of $-40^{\circ}C\;to\;80^{\circ}C$. For upstream channel transmission test in the EPON system were a Zig board and a burst mode receiver. Zenko-made optical module was used for the burst mode receiver by adding functions of serializer/deserializer and clock data recovery, a Virtex II pro20 chipset and Vitesse VSC7123 were used in the Zig board for characterizing the burst mode and in the clock data recovery chipset, respectively. Startup acquisition lock time and data acquisition lock time were measured to be 670ns and 400ns, respectively, in the upstream channel transmission of the EPON system adapting the $2{\times}32$ splitter fabricated in this work.