• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.71-78
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• 2013

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

• Korean Journal of Human Ecology
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• v.19 no.2
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• pp.245-256
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• 2010

The purpose of this study is on the effect of the Baduk play activity upon a child's intelligence, problem solving and delay of gratification. 68 participants (36 from the test group and 32 from the regulation group) were selected from 5 year old children who attend two elementary school annexed kindergartens for a pre-test and post-test in order to verify the effect of the Baduk play activity. The Baduk play activity was applied to the test group 3 times a week from the 3rd week of March, 2008 until the 3rd week of October, 2008. In this study, K-WPPSI, CPS and delay of gratification test were used to measure the effect of the activity. As a result, it can be construed that the Baduk play activity gives children a more positive influence upon their activity and overall IQ, ability of problem- solving and delay of gratification.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.807-810
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• 1998

This paper presents BIST (Built-in self-test) techniques for detection of path delay faults in digital circuits. In the proosed BIST schemes, the shift registers make possible to concurrently generate and compact the latched test data. Therefore the test time is reduced efficiently. By reordering the elements of th shifte register based on the information of the hamming distance of each memory elements in CUt, it is possible to increase the number of path delay faults detected robustly/non-robustly. Experimental results for ISCAS'89 benchmark circuits show the efficiency of the proposed BIST techniques.

• Journal of Positioning, Navigation, and Timing
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• v.9 no.2
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• pp.131-138
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• 2020

In this paper, we analyze the delay phenomenon that can occur when controlling an unmanned aerial vehicle using a camera and describe a solution to solve the phenomenon. The group of pictures (GOP) value is changed in order to reduce the delay according to the frame data size that can occur in the moving image data transmission. The appropriate GOP values were determined through experimental data accumulation and validated through camera self-test, system integration laboratory (SIL) verification test and system integration test.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.29 no.5D
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• pp.563-570
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• 2009

This study is aimed to analyze the overall effects of the additional delay caused by the vehicle in front of the queue, at the signal, to the total delay estimation. To estimate the average vehicle delay at the signalized intersection, as survey of the queue length at the intersection and traffic counts were conducted. As a result of this analysis, all of the three delay estimation methods turned out to be similar in that the estimation of the average delay for the test vehicle was less than 60 sec/vehicle. However, the average delay time for the vehicle in front of the queue only, was estimated at 60-70 sec/vehicle which is similar to the average delay of the test vehicle.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1161-1166
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• 1999

Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.

• Korean Journal of Child Studies
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• v.17 no.2
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• pp.221-233
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• 1996

The purpose of the present study was to investigate the effects of age, sex, cognitive style and reward presentation on delay of gratification. The subjects of this study were 120 children 4, 6 and 8 years of age attending preschool and an elementary school in Pusan. They were identified as impulsive or reflective according to their performance on Kagan's Matching Familiar Figures Test. The levels of reward presentation consisted of the reward which was presented physically and the reward which wasn't presented physically. Length of waiting time was recorded as the measure of maintenance of delay of gratification. The data of this study were analyzed with Two-way ANOVA, Duncan's Multiple Range Test. The major finding were as follows: (1) Delay time increased with age. (2) No sex difference is found in delay time. (3) Reflective children delayed longer than impulsive children in all age groups. (4) The reward which wasn't physically presented produced loner delay time than the reward which was physically presented in all age groups.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.51-59
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• 2010

Two logic transformations, De Morgan and re-substitution, are sufficient to convert a unate gate network (UGN) to a more general balanced inversion parity (BIP) network. Circuit classes of interest are discussed in detail. We prove that De Morgan and re-substitution transformations are test-set preserving for path delay faults. Using the results of this paper, we can easily show that a high-level test set for a function z that detects all path delay faults in any UGN realizing z also detects all path delay faults in any BIP realization of z.

• ETRI Journal
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• v.25 no.3
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• pp.187-194
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• 2003

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45 % over the conventional functional justification.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1710-1715
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• 2014

In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection.