• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.103-106
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• 2010

In this paper, the delay times were evaluated to develop highly reliable time-to-digital converter(TDC) in analog and digital delay element structures. The delay element can be designed by using current source or inverter. In case of using inverter, the number of inverter has to be controlled to adjust the delay time. And in case of using current source, the current for charging and discharging is controlled. When the current source is used the delay time of the delay element is not sensitive with varying the channel width of CMOS. However, when the inverter is used the delay time is directly related to the channel width of CMOS. Therefore to obtain good reliability in TDC circuit the delay element using current source is more stable compared to inverter in the viewpoint of the variation of fabrication process.

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.461-465
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• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.11
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• pp.859-865
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• 1991

The paper proposes a design of high-speed dynamic CMOS PLA (Programmable Logic Array) which performs stable circuit operation. The race problem which nay occur in a NOR-NOR implementation of PLA is free in the proposed dynamic CMOS PLA by delaying time between the clocks to the AND- and to the OR-planes. The delay element has the same structure as the product line of the longest delay in the AND p`ane. Therefore it is unnecessary to design the delay element or to calculate correct delay time. The correct delay generated by the delay element makes the dynamic CMOS PLA to perform correct and stable circuit operation. Theproposed dynamic CMOS PLA has few variation of switching delay with the increasing number of inputs or outputs in PLA. It is verified by SPICE circuit simulation that the proposed dynamic CMOS PLA has the better performance over existing dynamic CMOS PLA's.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.681-689
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• 2010

We will demonstrate a novel topology for the feedforward amplifier. This amplifier does not use a delay element thus providing an efficiency enhancement and a size reduction by employing a distributed element negative group delay circuit. The insertion loss of the delay element in the conventional feedforward amplifier seriously degrades the efficiency. Usually, a high power co-axial cable or a delay line filter is utilized for a low loss, but the insertion loss, cost and size of the delay element still acts as a bottleneck. The proposed negative group delay circuit removes the necessity of the delay element required for a broadband signal suppression loop. With the fabricated 2-stage distributed element negative group delay circuit with -9 ns of total group delay, a 0.2 dB of insertion loss, and a 30 MHz of bandwidth for a wideband code division multiple access downlink band, the feedforward amplifier with the proposed topology experimentally achieved a 19.4 % power added efficiency and a -53.2 dBc adjacent channel leakage ratio with a 44 dBm average output power.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.172-175
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• 2003

In this paper we propose a method fur the evaluation of the quality of service for VoIP services in NGN. Specifically, let us anatomize the elements of delay of a voice connection in the network in an end-to-end manner and investigate expected value at each point. We extract the delay time in each element in the network such as gateway, network node, and terminal equipment, and estimate an upper bound fur the tolerable delay in each element.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1041-1044
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• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.326-328
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• 2009

we an autotuning algorithm for PI controller with unknown plant. The proposed algorithm uses a saturation function and time delay element as a test signal. Since the integral element of PI controller reduces a phase margin and amplitude margin in the closed loop system, the closed loop system could be resulted in unstable with PI controller, To avoid unstable in the closed loop system with PI controller, the proposed algorithm identifies one point information in the 3rd quadrant of Nyquist plot with a time delay element. The proposed method improves an accuracy of one point identified information with one saturation function.

• Journal of ILASS-Korea
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• v.25 no.3
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• pp.119-125
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• 2020

In this paper, we used Helmholtz solver based on 3D finite element method to quantitatively analyze the effects of change of gain, time delay and time delay spread, which are the main variables of flame transfer function, on combustion instability in gas turbine combustor. The effects of the variable of flame transfer function on the frequency and growth rate, which are the main results of combustion instability, were analyzed by applying the conventional heat release fluctuation model and modified one considering the time spread. The analysis results showed that the change of gain and time delay in the same resonance mode affected the frequency of the given resonance modes as well as growth rate of the feedback instability, however, the effect of time delay spread was not relatively remarkable, compared with the dominant effect of time delay.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.8
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• pp.1534-1544
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• 2002

The TDCSA(Time Delay Control with Switching Action) method, which consists of Time Delay Control(TDC) and a switching action of sliding mode control(SMC), has been proposed as a promising technique in the robust control area, where the plant has unknown dynamics with parameter variations and substantial disturbances are preset. When TDCSA is applied to the plant with saturation nonlinearity, however, the so-called windup phenomena are observed to arise, causing excessive overshoot and instability. The integral element of TDCSA and the saturation element of a plant cause the windup phenomena. There are two integral effects in TDCSA. One is the integral effect occurred by time delay estimation of TDC. Other is the integral term of an integral sliding surface. In order to solve this problem, we have proposed an anti-windup scheme method for TDCSA. The stability of the overall system has been proved for a class of nonlinear system. Experiment results show that the proposed method overcomes the windup problem of the TDCSA.