• Journal of IKEEE
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• v.17 no.2
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• pp.168-175
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• 2013

The delay times due to the propagating of data on PCB depend on the shape and length of interconnection lines when memory controllers and high speed memories are soldered on the PCB. The dependency on the placement and routing on the PCB requires redesign of I/O logic or reconfiguration of the memory controller after the delay time is measured if the controller is programmable. In this paper, we propose architecture of configuring logic for the delay time estimation by writing and reading test patterns while initializing the memories. The configuration logic writes test patterns to the memory and reads them by changing timing until the correct patterns are read. The timing information is stored and the configuration logic configures the memory controller at the end of initialization. The proposed method enables easy design of systems using PCB by solving the problem of the mismatching caused by the variation of placement and routing of components including memories and memory controllers. The proposed method can be applied to high speed SRAM, DRAM, and flash memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.9
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• pp.2022-2028
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• 2015

SpaceWire is a standard for high-speed links and networks between spacecraft components, which was invented for better, cheaper and faster on-board data handling in spacecraft. The standard defines timecode and its distribution which can be used for time synchronization among the nodes in a SpaceWire network. A timecode output from the time master which provides standard time over a SpaceWire network travels through links and routers to reach every nodes. While traveling, a timecode suffers from transmission delay and jitter which cause some difference in time synchronization among nodes. In this work, a simulator was developed using OMNeT++ to simulate the operation of a SpaceWire network and some analyses were performed on the transmission delay and jitter accompanied with a transmission of a timecode. The result will be used in the near future for the research of a precise time synchronization technique over a SpaceWire network.

• Journal of the Korean Society of Safety
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• v.39 no.2
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• pp.38-43
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• 2024

Recently, with the expanding market for electronic devices and electric vehicles, secondary battery usage has been on the rise. Lithium-ion batteries are particularly popular due to their fast charging times and lightweight nature compared to other types of batteries. A secondary battery consists of four components: anode, cathode, electrolyte, and separator. Generally, the positive and negative electrode materials of secondary batteries are composed of an active material, a binder, and a conductive material. Acetylene Black (AB) is utilized to enhance conductivity between active material particles or metal dust collectors, preventing the binder from acting as an insulator. However, when recycling waste batteries that have been subject to high usage, there is a risk of fire and explosion accidents, as accurately identifying the characteristics of Acetylene Black dust proves to be challenging. In this study, the lower explosion limit for Acetylene Black dust with an average particle size of 0.042 ㎛ was determined to be 153.64 mg/L using a Hartmann-type dust explosion device. Notably, the dust did not explode at values below 168 mg, rendering the lower explosion limit calculation unfeasible. Analysis of explosion delay times with varying electrode gaps revealed the shortest delay time at 3 mm, with a noticeable increase in delay times for gaps of 4 mm or greater. The findings offer fundamental data for fire and explosion prevention measures in Acetylene Black waste recycling processes via a predictive model for lower explosion limits and ignition delay time.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.1
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• pp.79-83
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• 2004

This paper presents the performance analysis for CPL based design of a Low power digital neuroprocessor. We have verified the functionality of the components at the high level using Verilog and carried out the simulations in Silos. The components of the proposed digital neuroprocessor have also been verified at the layout level in LASI. The layouts have then been simulated and analyzed in Winspice for their timing characteristics. The result shows that the proposed digital neuroprocessor consistently consumes less power than other designs of the same function. It can also be seen that the proposed functions have lesser propagation delay and thus higher speed compared to the other designs.

• Journal of applied mathematics & informatics
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• v.26 no.1_2
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• pp.355-364
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• 2008

Under pathological stress stimuli, dynamics of a biological system can be changed by alteration of several components such as functional proteins, ultimately leading to disease state. These dynamics in disease state can be modeled using differential equations in which kinetic or system parameters can be obtained from experimental data. One of the most effective ways to restore a particular disease state of biology system (i.e., cell, organ and organism) into the normal state makes optimization of the altered components usually represented by system parameters in the differential equations. There has been no such approach as far as we know. Here we show this approach with a cardiac hypertrophy model in which we obtain the existence of the optimal parameters and construct an optimal system which can be used to find the optimal parameters.

• Journal of Korean Society for Quality Management
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• v.21 no.2
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• pp.17-26
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• 1993

Process fault diagnosis is a complicated matter because quality control problems can result from a variety of causes. These causes include problems with electrical components, mechanical components, human errors, job justification errors, and air conditioning influences. In order to make the system run smoothly with minimum delay, it is necessary to suggest heuristic remedies for the detected faults. Hence, this paper describes a heuristic methodology of fault diagnosis that is performed using statistical patterns generated by quality characteristics The proposed methodology is described briefly as follows: If a sample pattern generated by random variables is similar to the number of prototype patterns, the sample pattern may be matched by any prototype pattern among them to be resembled. This concept is based on the similarity between a sample pattern and the matched prototype pattern. The similarity is calculated as the weighted average of squared deviation, which is expressed as the difference between the relative values of standard normal distribution to be transformed by the observed values of quality characteristics in a sample pattern and the critical values of the corresponding ones in a matched prototype pattern.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.6
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• pp.584-591
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• 2004

The conventional analog-based firing circuit can be implemented by comparing a linearly decreasing periodic sawtooth waveform synchronized to the ac supply, with a control signal corresponding to the desired converter delay angle. This circuit requires a large number of passive components (resistance and capacitor) and careful adjustment of the synchronization circuity. In this paper a novel firing circuit is proposed for thyristor switch. The proposed circuit is implemented by using digital components(FPGA, A/D, and DSP etc.) on the basis of the analog cosine method.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.506-508
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• 1999

In the distributed control systems where the control components, controllers and sensors are distributed on a communications network, there exist network time delays on communication lines between the system components. This paper deals with the ramp tracking controller design issue for such systems. Time delay terms are converted into the rational terms using Pade approximation method and the system is augmented with two integrators for ramp tracking. For this system, $\mu$-controller design method, which enables to meet not only performance requirements but robust stabilities simultaneously, is employed.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.57-60
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• 2001

In the distributed control systems where the control components, controllers and sensors are distributed on a communications network, there exit network time delays on communication lines between the system components. This paper deals with the 2 D.O.F. ramp tracking controller design issue for such system. Time delay terms are converted into rational terms using Pade approximation method and the system is augmented with two integrators for ramp tracking. For this system, $\mu$-controller design method, which enables to meet not only performance requirements but robust stabilities simultaneously, is employed.

• Proceedings of the KIEE Conference
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• 1999.07b
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• pp.951-953
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• 1999

In the distributed control systems where the control components, controllers and sensors are distributed on a communications network, there exist network time delays on communication lines between the system components. This paper deals with the ramp tracking controller design issue for such systems. Time delay terms are converted into the rational terms using Pade approximation method and the system is augmented with two integrators for ramp tracking. For this system, ${\mu}$-controller design method, which enables to meet not only performance requirements but robust stabilities simultaneously, is employed.