• Journal of the Korean Operations Research and Management Science Society
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• v.22 no.3
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• pp.145-162
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• 1997

This paper an analytical model for estimating packet waiting times at stations in the DQDB network, where the most upstream station is saturated. This model is useful in comparing the extreme unfairness which downstream stations experience due to their geographical locations in accessing the medium. Each station is modeled as an M/G/1, where the service time is defined to be the time a packet spends in the transmission buffer. The service time is decomposed into five components, and in turn, the first and second moment of each component are derived in three different modes of operation. Simulation experiments are presented for model validation and results are discussed.

• Proceedings of the Korean Radioactive Waste Society Conference
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• 2004.02a
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• pp.96-105
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• 2004

The decommissioning project of the KRR 1 & 2 was started in January 1997. The actual decommissioning activity was started at the RI production facility and was finished at the end of 2002. The dismantling works of all components including the reactor structure of the KRR-2 was started in January, 2003 and will be carried out for 2 years till the end of 2004. The project schedule is estimated to delay for 4∼5 months beyond the original plan because of delaying on the cutting of thermal column nose and removal of the graphite bricks, but it may be caught up during the removal working of concrete from biological shielding structure. This paper summarizes the general status of the KRR 1 & 2 and decommissioning activities.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.33-39
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• 1998

A queueing model for performance evaluation of finite buffered inter-node communication system is proposed in this paper. Each components are modeled as M/M/I/B queues to obtain the steady state probabilities and ar-rival rate and to analyze finite buffer behavior, The overall sysrem is integrated as series queues with blocking. Average delay and throughput are the performance measures studied in this analysis. The analytical results are first validated through simulation. Next, the effect of buffer length is discussed using the proposed model.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.354-358
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• 2001

Cosim (Hardware and Software Co-Simulator) is a JavaBeans-based simulation tool fur validating systems architecture and estimating performance of web applications. Cosim has four components: Modeler, Translator, Engine and Scenario. Users start from Modeler to describe systems architecture in UML(Unified Modeling Language) deployment diagram, and then specify hardware & software performance parameters such as execution delay, network topology, and frame size. All information specified on Modeler are sent to Translator, and then automatically converted to Java programs. Scenario is responsible to run the Java program and produce results in text reports and graphs. Developers can reduce development time and cost by validating systems architecture of web applications before the actual deployment.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.680-683
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• 1996

The dynamics of the vehicle system has highly nonlinear components such as an engine, a torque converter and variable road condition. This thesis proposes a Fuzzy Logic Algorithm that shows better control performance than Antiwindup PI in the highly nonlinear vehicle system. Traction Control System(TCS), which adjusts throttle valve opening by Fuzzy Logic Algorithm improves vehicle drivability, steerability and stability when vehicle is starting and cornering. When a throttle valve is opened at large degree, Fuzzy Logic Algorithm shows better performances like a small settling time and a small oscillation than Antiwindup PI in simulation. The decreased desired slip ratio improves steerability in the simulation when a vehicle is cornering. The Fuzzy Logic Algorithm has been tested by a 1/5-scale vehicle for tracking the constant desired velocity.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1606-1616
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• 1989

In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2161-2163
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• 2004

This paper focuses on congestion control for ATM network with uncertain time-variant delays. The time-variant delays can be distinguished into two distinct components. The first one that is represented by time-variant queueing delays in the intermediate switches is occurred in the return paths of RM cells. The next one is a forward path delay. It is solved by the VBR Model which quantifies the data propagation from the sources to the switch. Robust $H_{\infty}$ control is studied for solving congestion problem with norm-bounded time-varying uncertain parameters. The suitable robust $H_{\infty}$ controller is obtained from the solution of a convex optimization problem including terms of LMIs.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.267-268
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• 2008

TD-SCDMA is considered as an innovative Chinese 3G technology adopted by the ITU for the IMT-2000 family. TD-SCDMA combines TDMA and CDMA components to provide more efficient use of radio resources. According to the traffic volume and activity level, the operation mode of a mobile terminal can change from one state to other states. This paper focuses on the problem of recovery delay from inactive states, and proposes a resource management algorithm, which holds some resources for rapid recovery of service after the service determines to release the dedicated resources.

• Journal of Mechanical Science and Technology
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• v.17 no.12
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• pp.2087-2098
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• 2003

The development of numerical mathematical model to calculate both the static and dynamic characteristics of a multi-shaft gas turbine consisting of a single combustion chamber, including advanced cycle components such as intercooler and regenerator is presented in this paper. The numerical mathematical model is based on the simplified assumptions that quasi-static characteristic of turbo-machine and injector is used, total pressure loss and heat transfer relation for static calculation neglecting fuel transport time delay can be employed. The supercharger power has a cubical relation to its rotating velocity. The accuracy of each calculation is confirmed by monitoring mass and energy balances with comparative calculations for different time steps of integration. The features of the studied gas turbine scheme are the starting device with compressed air volumes and injector's supercharging the air directly ahead of the combustion chamber.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.5
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• pp.1-10
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• 1998

In this paper, a new hardware-software patitioning algorithm is presented, in which the system behavioral description containing a mixture of hardware and softwae components is partitioned into the hardware part and the software part. In this research, new techniques to optimally partition a mixed system under certain specified constaints such as performance, area, and delay, have been developed. During the partitioning process, the overhead due to the communication between the hardware and software parts are considered. New featues have been added to adjust the hierarchical level of partitioning. Power consumption, memory cost, and the effect of pipelining can also be considered during partitioning. Another new feature is the ability to partition a DSP system under throughput constraints. This feature is important for real time processing. The developed partitioning system can also be used to evaluate various design alternatives and architectures.