• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.349-352
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• 2001

In this paper, novel device structure in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA) for ultra pn junction formation. Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20 nm for arsenic dosage (2$\times$10$^{14}$ $\textrm{cm}^2$), excimer laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.185-188
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• 2001

Chemical mechanical polishing(CMP) process is widely used for global planarization of inter-metal dielectric (IMD) layer and inter-layer dielectric (ILD) for deep sub-micron technology. However, as the IMD and ILD layer gets thinner, defects such as micro-scratch lead to severe circuit failure, which affect yield. In this paper, for the improvement of CMP Process, deionized water (DIW) pressure, purified $N_2$ (P$N_2$) gas, slurry filter and high spray bar were installed. Our experimental results show that DIW pressure and P$N_2$ gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. Also, the filter installation in CMP polisher could reduce defects after CMP process, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. However, the slurry filter is impossible to prevent defect-causing particles perfectly. Thus, we suggest that it is necessary to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of slurry filter. Finally, we could expect the improvements of throughput, yield and stability in the ULSI fabrication process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.41-44
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• 2003

As the device feature size is reduced to the deep sub-micron regime, the chemical mechanical polishing (CMP) technology is widely recognized as the most promising method to achieve the global planarization of the multilevel interconnection for ULSI applications. However, cost of ownership (COO) and cost of consumables (COC) were relatively increased because of expensive slurry. In this paper, the effects of different slurry composition on the oxide CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity. We prepared the various kinds of slurry. In order to save the costs of slurry, the original slurry was diluted by de-ionized water (DIW). And then, alunima abrasives were added in the diluted slurry in order to promote the mechanical force of diluted slurry.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12B
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• pp.1548-1555
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• 2011

In ultra-deep submicron technology, minimization of propagation delay and power consumption on buses is one of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. Most of the previous works on bus encoding are targeted either to minimize the bus switching or minimize the crosstalk delay, but not both. This paper proposes a new bus encoding scheme which can adaptively select one of functions "invert" and "logic-convert" according the number of bus switching on an encoded 4-bit cluster. This scheme leads to minimization of both crosstalk and bus switching. In experiment result, our proposed encoding technique consumes about 25% less power over the previous, while completely eliminating the crosstalk delay.

• Transactions on Electrical and Electronic Materials
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• v.5 no.5
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• pp.169-172
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• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.51-55
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• 2007

This paper investigates the subthreshold behavior of Fin Field Effect Transistor (FinFET). The FinFET is considered to be an alternate MOSFET structure for the deep sub-micron regime, having excellent device characteristics. As the channel length decreases, the study of subthreshold behavior of the device becomes critically important for successful design and implementation of digital circuits. An accurate analysis of subthreshold behavior of FinFET was done by simulating the device in a 3D process and device simulator, Taurus. The subthreshold behavior of FinFET, was measured using a parameter called S-factor which was obtained from the $In(I_{DS})\;-\;V_{GS}$ characteristics. The value of S-factor of devices of various fin dimensions with channel length $L_g$ in the range of 20 nm - 50 nm and with the fin width $T_{fin}$ in the range of 10 nm - 40 nm was calculated. It was observed that for devices with longer channel lengths, the value of S-factor was close to the ideal value of 60 m V/dec. The S-factor increases exponentially for channel lengths, $L_g\;<\;1.5\;T_{fin}$. Further, for a constant $L_g$, the S factor was observed to increase with $T_{fin}$. An empirical relationship between S, $L_g$ and $T_{fin}$ was developed based on the simulation results, which could be used as a rule of thumb for determining the S-factor of devices.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.248-248
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• 1999

현재 반도체 공정에서 사용하는 건식식각 공정은 고밀도 프라즈마를 사용한 플라즈마 장비를 사용하는 경향이 증대되고 있으며 이와 같은 고밀도 플라즈마 장비의 사용은 반도체 소자의 최소 선폭(CD)이 deep sub-micron으로 감소하고 반면 실리콘 웨이퍼의 크기는 8인치 직경이상으로 증가하여 가고 있어서 그 필요성이 더욱 더 증가되고 있다. 특히 TFT-LCD를 비롯한 PDP, 그리고 FED 등과 같은 여러 가지 형태의 평판 디스플레이의 제조공정에 있어서도 실리콘 기판에 비하여 대면적의 기판을 이용하고 또한 사각형 형태의 시편공정이 요구되므로 평판 디스플레이에서도 고밀도의 균일한 플라즈마 유지가 중요하다. 따라서, 본 실험에서는 여러 가지 형태의 영구자석 및 전자석의 세기 및 배열이 유도결합형 플라즈마에 미치는 효과(plasma&etch uniformity, etch rate, etc.)를 살펴보기 위해서, 유도결합형 플라즈마 chamber(210mm$\times$210mm) 내부에 magnetic cusping을 위한 영구자석용 하우스를 제작하여 표면에서 3000Gauss의 자장세기를 갖는 소형영구자석을 부착하였으며,외벽에는 chamber와 같이 사각형태로 40회 감겨진 50cm$\times$50cm 의 크기로 chamber 상하에 1개씩 Helmholtz 코일 형태로 설치하였다. 식각가스로는 Cl2, HBr, 그리고 BCl3 gas를 이용하여 axial magnet과 multidipole magnet 유무에 따른 반응성 gas의 polysilicon 식각특성을 살펴보았으며, 또한 electrostatic probe(ESP, Hiden Analytic미)를 이용하여 이들 반응성 gas에 대한 magnetically enhanced inductively coupled plasma의 특성분석을 수행하였따. Cl2, HBr, BCl3의 반응성 식각가스 조합을 이용하여 polysilicon의 식각속도 및 식각선택도를 관찰한 결과, 어떠한 자장도 가하지 않은 경우에 비해 gas의 분해율이 가장 높은 영구자석과 전자석의 조합에서 가장 높은 식각도가 관찰되었다. 특히 pure Cl2 플라즈마의 경우, Axial 방향의 전자석만을 가한 경우 식각속도에 있어서는 큰 증가를 보였으나, 식각균일도(식각균일도:8.8%)는 다소 감소하였으며, Axial 방향의 전자석과 영구자석을 조합한 경우 가장 높은 식각속도를 얻었으며, 식각균일도는 Axial 방향의 전자석만을 사용하였을 경우와 비교하여 향상되었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.185-188
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• 2001

Chemical mechanical polishing(CMP) process is widely used for global planarization of inter-metal dielectric (IMD) layer and inter-layer dielectric (ILD) for deep sub-micron technology. However, as the IMD and ILD layer gets thinner, defects such as micro-scratch lead to severe circuit failure, which affect yield. In this paper, for the improvement of CMP process, deionized water (DIW) pressure, purified $N_2 \; (PN_2)$ gas, slurry filter and high spray bar were installed. Our experimental results show that DIW pressure and $PN_2$ gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. Also, the filter installation in CMP polisher could reduce defects after CMP process, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. However, the slurry filter is impossible to prevent defect-causing particles perfectly. Thus, we suggest that it is necessary to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of slurry filter. Finally, we could expect the improvements of throughput, yield and stability in the ULSI fabrication process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.50-53
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• 2003

CMP (chemical mechanical polishing) process remained to solve several problems in deep sub-micron integrated circuit manufacturing process. especially consumables (polishing pad, backing film, slurry, pad conditioner), one of the most important components in the CMP system is the slurry. Among the composition of slurries (buffer solution, bulk solution, abrasive particle, oxidizer, inhibitor, suspension, antifoaming agent, dispersion agent), the abrasive particles are important in determining polish rate and planarization ability of a CMP process. However, the cost of abrasives is still very high. So, in order to reduce the high COO (cost of ownership) and COC (cost of consumables) in this paper, we have collected the silica abrasive powders by filtering after subsequent CMP process for the purpose of abrasive particle recycling. And then, we have studied the possibility of recycle of reused silica abrasive through the analysis of particle size and hardness. Also, we annealed the collected abrasive powders to promote the mechanical strength of reduced abrasion force. Finally, we compared the CMP characteristics between self-developed KOH-based silica abrasive slurry and original slurry. As our experimental results, we obtained the comparable removal rate and good planarity with commercial products. Consequently, we can expect the saving of high cost slurry.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.5
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• pp.191-195
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• 2002

Chemical mechanical Polishing (CMP) process is widely used for the global planarization of inter-metal dielectric (IMD) layer and inter-layer dielectric (ILD) for deep sub-micron technology. However, as the IMD and ILD layer gets thinner, defects such as micro-scratch lead to severe circuit failure, which affect yield. In this paper, for the improvement of CMP process, deionized water (DIW) pressure, purified $N_2$ ($PN_2$) gas, point of use (POU) slurry filler and high spray bar (HSB) were installed. Our experimental results show that DW pressure and P$N_2$ gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. Also, the filter installation in CMP polisher could reduce defects after CMP process, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. However, the slurry filter is impossible to prevent defect-causing particles perfectly. Thus, we suggest that it is necessary to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of slurry filter Finally, we could expect the improvements of throughput, yield and stability in the ULSI fabrication process.