• Title/Summary/Keyword: data decimation

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A Study on the Precise Distance Measurement for Radar Level Transmitter of FMCW Type using Correlation Anaysis Method (상관분석법을 이용한 FMCW 타입 레이더 레벨 트랜스미터의 정밀 거리 측정에 관한 연구)

  • Ji, Suk-Joon;Lee, John-Tark
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.7
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    • pp.1024-1031
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    • 2012
  • In this paper, FMCW type radar level transmitter using correlation analysis method is implemented for precise distance measurement of cargo tank. FMCW type radar level transmitter is the device for distance measurement which calculates the distance by analyzing the beat frequency, that is, the frequency difference between Tx and RX signal from radar antenna using Fast Fourier Transform(FFT), but compensated algorithm like Zoom FFT is needed for the improvement of the frequency precision because the frequency precision of FFT is limited depending on sampling frequency and the number of sampling data. In case of Zoom FFT, the number of sampling data and noisy signal are the main factor influencing the measurement accuracy of Zoom FFT like FFT. Therefore, in order to overcome the limited environment and achieve the precise measurement, correlation coefficient is used for the distance measurement and the errors of measurement are verified to be in the range of ${\pm}1mm$.

A Study on a Lossless Compression Scheme for Cloud Point Data of the Target Construction (목표 구조물에 대한 점군데이터의 무손실 압축 기법에 관한 연구)

  • Bang, Min-Suk;Yun, Kee-Bang;Kim, Ki-Doo
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.48 no.5
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    • pp.33-41
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    • 2011
  • In this paper, we propose a lossless compression scheme for cloud point data of the target construction by using doubleness and decreasing useless information of cloud point data. We use Hough transform to find the horizontal angle between construction and terrestrial LIDAR. This angle is used for the rotation of the cloud point data. The cloud point data can be parallel to x-axis, then y-axis doubleness is increased. Therefore, the cloud point data can be more compressed. In addition, we apply two methods to decrease the number of cloud point data for useless information of them. One is decimation of the cloud point data, the other is to extract the range of y-coordinates of target construction, and then extract the cloud point data existing in the range only. The experimental result shows the performance of proposed scheme. To compress the data, we use only the position information without additional information. Therefore, this scheme can increase processing speed of the compression algorithm.

Prediction of time-series underwater noise data using long short term memory model (Long short term memory 모델을 이용한 시계열 수중 소음 데이터 예측)

  • Hyesun Lee;Wooyoung Hong;Kookhyun Kim;Keunhwa Lee
    • The Journal of the Acoustical Society of Korea
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    • v.42 no.4
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    • pp.313-319
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    • 2023
  • In this paper, a time series machine learning model, Long Short Term Memory (LSTM), is applied into the bubble flow noise data and the underwater projectile launch noise data to predict missing values of time-series underwater noise data. The former is mixed with bubble noise, flow noise, and fluid-induced interaction noise measured in a pipe and can be classified into three types. The latter is the noise generated when an underwater projectile is ejected from a launch tube and has a characteristic of instantaenous noise. For such types of noise, a data-driven model can be more useful than an analytical model. We constructed an LSTM model with given data and evaluated the model's performance based on the number of hidden units, the number of input sequences, and the decimation factor of signal. It is shown that the optimal LSTM model works well for new data of the same type.

An Automatic Extraction Algorithm of Structure Boundary from Terrestrial LIDAR Data (지상라이다 데이터를 이용한 구조물 윤곽선 자동 추출 알고리즘 연구)

  • Roh, Yi-Ju;Kim, Nam-Woon;Yun, Kee-Bang;Jung, Kyeong-Hoon;Kang, Dong-Wook;Kim, Ki-Doo
    • 전자공학회논문지 IE
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    • v.46 no.1
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    • pp.7-15
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    • 2009
  • In this paper, automatic structure boundary extraction is proposed using terrestrial LIDAR (Light Detection And Ranging) in 3-dimensional data. This paper describes an algorithm which does not use pictures and pre-processing. In this algorithm, an efficient decimation method is proposed, considering the size of object, the amount of LIDAR data, etc. From these decimated data, object points and non-object points are distinguished using distance information which is a major features of LIDAR. After that, large and small values are extracted using local variations, which can be candidate for boundary. Finally, a boundary line is drawn based on the boundary point candidates. In this way, the approximate boundary of the object is extracted.

Memory Reduction Method of DIT-based IFFT Bit-Reversal (DIT 기반 IFFT의 Bit-Reversal 메모리 감소 기법)

  • Kim, Jun-Ho;Piao, Zheyan;Cho, Kyung-Ju;Chung, Jin-Gyun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.5
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    • pp.66-73
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    • 2015
  • IFFT is one of the key components in OFDM-based communication systems. In this paper, we propose a new memory efficient IFFT design method for OFDM-based communication systems, based on a mapping of three IFFT input signals which consist of modulated data, pilot and null signals. The proposed method focuses on reducing the memory size in the bit-reversal block which requires the largest number of memory cells in IFFT architectures. To reduce the memory size, we propose a selection mapping method based on decimation-in-time (DIT) algorithm. It is shown that the proposed method achieves a memory reduction of about 50% compared to conventional methods.

Implementation of sigma-delta A/D converter IP for digital audio

  • Park SangBong;Lee YoungDae
    • Proceedings of the IEEK Conference
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    • summer
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    • pp.199-203
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    • 2004
  • In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

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Implementation of Low Complexity FFT, ADC and DAC Blocks of an OFDM Transmitter Receiver Using Verilog

  • Joshi, Alok;Gupta, Dewansh Aditya;Jaipuriyar, Pravriti
    • Journal of Information Processing Systems
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    • v.15 no.3
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    • pp.670-681
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    • 2019
  • Orthogonal frequency division multiplexing (OFDM) is a system which is used to encode data using multiple carriers instead of the traditional single carrier system. This method improves the spectral efficiency (optimum use of bandwidth). It also lessens the effect of fading and intersymbol interference (ISI). In 1995, digital audio broadcast (DAB) adopted OFDM as the first standard using OFDM. Later in 1997, it was adopted for digital video broadcast (DVB). Currently, it has been adopted for WiMAX and LTE standards. In this project, a Verilog design is employed to implement an OFDM transmitter (DAC block) and receiver (FFT and ADC block). Generally, OFDM uses FFT and IFFT for modulation and demodulation. In this paper, 16-point FFT decimation-in-frequency (DIF) with the radix-2 algorithm and direct summation method have been analyzed. ADC and DAC in OFDM are used for conversion of the signal from analog to digital or vice-versa has also been analyzed. All the designs are simulated using Verilog on ModelSim simulator. The result generated from the FFT block after Verilog simulation has also been verified with MATLAB.

Automatic Recognition of Analog and Digital Modulation Signals (아날로그 및 디지털 변조 신호의 자동 인식)

  • Seo Seunghan;Yoon Yeojong;Jin Younghwan;Seo Yongju;Lim Sunmin;Ahn Jaemin;Eun Chang-Soo;Jang Won;Nah Sunphil
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.1C
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    • pp.73-81
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    • 2005
  • We propose an automatic modulation recognition scheme which extracts pre-defined key features from the received signal and then applies equal gain combining method to determine the used modulation. Moreover, we compare and analyze the performance of the proposed algorithm with that of decision-theoretic algorithm. Our scheme extracts five pre-defined key features from each data segment, a data unit for the key feature extraction, which are then averaged over all the segments to recognize the modulation according to the decision procedure. We check the performance of the proposed algorithm through computer simulations for analog modulations such as AM, FM, SSB and for digital modulations such as FSK2, FSK4, PSK2, and PSK4, by measuring recognition success rate varying SNR and data collection time. The result shows that the performance of the proposed scheme is comparable to that of the decision-theoretic algorithm with less complexity.

Design and Fabrication of a Processing Element for 2-D Systolic FFT Array (고속 퓨리어변환용 2차원 시스토릭 어레이를 위한 처리요소의 설계 및 제작)

  • Lee, Moon-Key;Shin, Kyung-Wook;Choi, Byeong-Yoon;,
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.3
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    • pp.108-115
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    • 1990
  • This paper describes the design and fabrication of a processing element that will be used as a component in the construction of a two dimensional systolic for FFT. The chip performs data shuffling and radix-2 decimation-in-time (DIT) butterfly arithmetic. It consists of a data routing unit, internal control logic and HBA unit which computes butterfly arithmetic. The 6.5K transistors processing element designed with standard cells has been fabricated with a 2u'm double metal CMOS process, and evaluated by wafer probing measurements. The measured characteristics show that a HBA can be computed in 0.5 usec with a 20MHz clok, and it is estimated that the FFT of length 1024 can be transformed in 11.2 usec.

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A New PAPR Reduction Methods in OFDM by Combining SLM and PTS (SLM과 PTS 방식의 혼합에 의한 OFDM 신호에서의 PAPR 새로운 감소 기법)

  • Kee Jong-Hae;Kim Myoung-Je;Ryu Jeong-Woong;Kim Sung-Soo
    • The Journal of the Korea Contents Association
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    • v.6 no.1
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    • pp.1-7
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    • 2006
  • This paper proposes a new method that reduces the complexity of the combined system, which consists of the selective mapping(SLM) and the partial transmit sequence(PTS) in the Orthogonal Frequency Division Multiplexing(OFDM). In order to reduce the Peak-to-Average Power Ratio(PAPR), many techniques have been developed such as SLM and PTS. and their combined systems. However the method that simply combines PTS and SLM to improve the effectiveness of a system increases the complexity of calculation. The scheme employed in this research suggests a system that combines PTS and SLM reducing the complexity via the N($N=2^n$)-point inverse fast Fourier transforms(IFFT), which uses the decimation in time domain not only to improve PAPR but also to reduce the amount of calculation. The proposed method reduces the complexity by multiplying a phase sequence and a subblock index to the data sequences in the middle of IFFT, which yields an optimal sequence with minimal PAPR. The superiority of the proposed method is demonstrated by simulation results and analysis.

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