• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.486-495
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• 2006

In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.

• Journal of IKEEE
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• v.22 no.4
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• pp.1006-1011
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• 2018

This paper proposes a three level buck converter utilizing multi-bit flying capacitor voltage control. The conventional three-level buck converter can not control the flying capacitor voltage, so that the operation is unstable or the circuit for controlling the flying capacitor voltage can not be applied to the PWM mode. Also when the load current is increased, an error occurs in the inductor voltage. The proposed structure can control the flying capacitor voltage in PWM mode by using differential difference amplifier and common mode feedback circuit. In addition, this paper proposes a 3bit flying capacitor voltage control circuit to optimize the operation of the three level buck converter depending on the load current, and a triangular wave generation circuit using the schmitt trigger circuit. The proposed 3-level buck converter is designed in $0.18{\mu}m$ CMOS process and has an input voltage range of 2.7V~3.6V and an output voltage range of 0.7V~2.4V. The operating frequency is 2MHz, the load current range is 30mA to 500mA, and the output voltage ripple is measured up to 32.5mV. The measurement results show a maximum power conversion efficiency of 85% at a load current of 130 mA.

• Korean Chemical Engineering Research
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• v.47 no.5
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• pp.558-564
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• 2009

POF(Polymer optical fiber) offers advantages of lighter, inexpensive, and easier to use over GOF(glass optical fiber). Its higher transmission loss and low bandwidth, however, make it suitable only for short distance networking such as LAN. The polymer materials and its synthesis technology of low transmission loss and the broader application for flexible POF are the two of many critical areas to be investigated more. In the current study, low-noise POF modules are developed and optimized with a low noise amplifier and low cost LED of 650 nm. In order to demonstrate the dynamic characteristics of the POF module for optical communication and sensing, we have built an image transfer module, optical transmission speed measurement module, optical transceiver for RS-232, and sound-transfer module, and the signal characteristics of them are evaluated. It is found that the module can be readily used for a quick and simple measurement of optical transfer speed. With help of analog amplifier, LED, and PD, sound and image transfers through a maximum 60 m optical waveguide have been confirmed. Real-time data transfer was also demonstrated in PID control, which is thought to be valuable to industrial plant design and control.

• 전자공학회논문지 IE
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• v.45 no.1
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• pp.31-37
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• 2008

A Wibro RF down converter of 2.3GHz band is designed and implemented in this paper. The problems that can occur in the receiver LNA(Low Noise Amplifier) to minimize additional purposes. In addition, 2.3GHz band from the 75 MHz downward to minimize the losses in the process, transform and improve efficiency, and achieve stable characteristics can be used to make high frequency characteristics of the device. Wibro repeater uses a TDMA(Time Division Multiplexing Access) method is needed because the RF switch. Production criterion specification, the input voltage from +8 V 1.2A of current consumption, 60dB gain and the noise figure of less than 2.5dB, VSWR(Voltage Standing Wave Ratio) less than 1.5, more than IMD(Inter Modulation Distortion) 60dB satisfied. Environmental conditions ($-20^{\circ}C$ to $70^{\circ}C$) to pass the test of reliability in a long time, that seemed crafted Wibro down converter be applied to the Wibro repeater.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.1-9
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• 2006

In this paper, a couple of 10Gb/s transimpedance amplifiers are realized in a 0.18um standard CMOS technology for optical communication applications. First, the voltage-mode inverter TIA(I-TIA) exploits inverter input configuration to achieve larger effective gm, thus reducing the input impedance and increasing the bandwidth. I-TIA demonstrates $56dB{\Omega}$ transimpedance gain, 14GHz bandwidth for 0.25pF photodiode capacitance, and -16.5dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. However, both its inherent parasitic capacitance and the package parasitics deteriorate the bandwidth significantly, thus mandating very judicious circuit design. Meanwhile, the current-mode RGC TIA incorporates the regulated cascade input configuration, and thus isolates the large input parasitic capacitance from the bandwidth determination more effectively than the voltage-mode TIA. Also, the parasitic components give much less impact on its bandwidth. RGC TIA provides $60dB{\Omega}$ transimpedance gain, 10GHz bandwidth for 0.25pF photodiode capacitance, and -15.7dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. Main drawback is the power dissipation which is 4.5 times larger than the I-TIA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.126-142
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• 2016

This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2747-2753
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• 2011

In this paper, a PWM current-mode DC-DC boost converter for mobile phone flash application has been proposed. The converter which is operated with 5 Mhz high switching frequency is capable of reducing mounting area of passive devices such as inductor and capacitor, consequently is suitable for compact mobile phones. This boost converter consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. Meanwhile, the control block consists of pulse width modulator, error amplifier, oscillator etc. Proposed boost converter has been designed and verified in a $0.5\;{\mu}m$ 1-poly 2-metal CMOS process technology. Simulation results show that the output voltage is 4.26 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 Khz driven converter when the duty ratio is 0.15.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.