• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.397-398
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• 2013

Fairchild Green Mode off line buck switch for low standby power consumption and high reliability is presented. By reducing operating current and optimizing switching frequency, 20mW power consumption is achieved. High performance trans-conductance amplifier and green mode function improve the ripple and regulation in the output voltage. The conventional $FPS^{TM}$ buck and novel Fairchild buck switch are compared to show the improvement of performance. Experimental results are showed using 2W evaluation board.

• Journal of the Optical Society of Korea
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• v.14 no.3
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• pp.240-244
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• 2010

In this work, we used PWM sampling for demodulation of a fiber-optic interferometric current transformer. The interference signal from a fiber-optic CT is sampled with PWM triggers that produce a 90-degree phase difference between two consecutively sampled signals. The current-induced phase is extracted by applying an arctangent demodulation and a phase unwrapping algorithm to the sampled signals. From experiments using the proposed demodulation, we obtained phase measurement accuracy and a linearity error, in AC current measurements, of ~2.35 mrad and 0.18%, respectively. The accuracy of the proposed method was compared with that of a lock-in amplifier demodulation, which showed only 0.36% difference. To compare the birefringence effects of different fiber-optic sensor coils, a flint glass fiber and a standard single-mode fiber were used under the same conditions. The flint glass fiber coil with a Faraday rotator mirror showed the best performance. Because of the simple hardware structure and signal processing, the proposed demodulation would be suitable for low-cost over-current monitoring in high voltage power systems.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.9
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• pp.34-40
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• 1999

In order to establish the design technique of the robust current controller in d.c series wound motor driver system, this paper proposes a method of the compensated Bang-Bang current control using d.c series wound motor driver system under the improperly variable load to get minimum time for the torque control. The compensated Bang-Bang current controller structure is simpler than that of PID plus Bang-Bang controller. This paper shows that a general 16 bits microprocessor is efficiently used to implement such an algorithm. The calculation time of software is extremely small when compared with that of conventional PID plus Bang-Bang controller. Both nonlinear operating characteristics of digital switching elements and describing function methods are used for the analysis and synthesis. Real-time implementation of the compensated Bang-Bang current controller is achieved. The concept of design strategy of the control and the PWM waveform generation algorithms are presented in this paper.

• Journal of IKEEE
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• v.20 no.2
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• pp.167-170
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• 2016

Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.

• ETRI Journal
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• v.36 no.3
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• pp.352-360
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• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.10
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• pp.3917-3922
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• 2010

In this paper, 3 stage amplifier MMIC was designed and fabricated with U-band optimized epitaxal pHEMT that produced by large signal characterization and modeling for 60 GHz band. The pHEMT used in this paper, the gate $0.12\;{\mu}m$ length and total gate width of $100\;{\mu}m$, $200\;{\mu}m$ has been modeled using the large signal designed with negative feedback and MCLF instead of MIM capacitor for improving stability. Fabricated MMIC $2.5{\times}1.5mm^2$ size, current about 40 mA, operating frequency 59.5~60.5 GHz, gain 19.9~18.6 dB, input matching characteristics -14.6~-14.7 dB, output matching characteristics -11.9~-16.3 dB and output -5 dBm characteristics were obtained.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6A
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• pp.697-704
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• 2004

This paper describes the design and fabrication of an MMIC variable gain LNA for 5GHz wireless LAN applications, using 0.5${\mu}{\textrm}{m}$ gate length GaAs MESFET transistors. The advantages of high gain and low noise performance of E-MESFETS and excellent linear performance of D-MESFETS are combined as a cascode topology in this design. Behavioral model equations are derived from the MESFET nonlinear current voltage characteristics by using Turlington's asymptote method in a cascode configuration. Using the behavioral model equations, a 4${\times}$50${\mu}{\textrm}{m}$ E-MESFET as a common source amplifier and a 2${\times}$50${\mu}{\textrm}{m}$ D-MESFET as a common gate amplifier are determined for the cascode amplifier. The fabricated variable gain LNA shows a noise figure of 2.4dB, variable gain range of more than 17dB, IIP3 of -4.8dBm at 4.9GHz, and power consumption of 12.8mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.53-60
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• 2005

Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.409-412
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• 2002

The LNA(Low Noise Amplifier) is designed for use in low cost commercial application covered fully IMT-2000 band(1920~2170MHz, BW=250MHz). It is optimized source inductance for source lead and designed to equivalent etched line. The LNA uses a high pass impedance matching network for noise match and simple structure. The bias circuit designs have been made self-biased with a negative voltage applied to gate. The power supply voltage is 8V, total current is 180mA. The LNA is biased at a Vgs of -0.4, Vds of 4V for first stage and Vds of 5V for second stage. The LNA is designed competitively for commercial product specification. The measured gain and noise figure of the completed amplifier was 20dB and 1dB, respectively. Also, input VSWR, P1dB and gain flatness was measured of 1.14 ~ l.3dB, 22.4dBm and $\pm$0.45dB, respectively. The designed LNA can be used for commercial product.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.301-306
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• 2015

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a $0.25{\mu}m$ GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the $3{\times}3-mm^2$ QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses ($S_{11}$ and $S_{22}$) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is $1.1{\times}0.9mm^2$. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.