• Journal of the Korean Magnetics Society
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• v.5 no.5
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• pp.790-794
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• 1995

Differential equations governing dynamic behavior of toroid-shaped ferro-magnetic material having a small gap of uniform width were derived incorporating Maxwell equations of electromagnetic induction relevent to the system and Newtonian equation of motion. Once the external uniform magnetic field was applied within the material through dc-circuit around the toroid, gap begin to change which lead to the abrupt variation of field in the material and gap according to the differential equations already derived. Characteristics of current and electromotive force with respect to time in the circuit consisting of inductance and resistance in series could be predicted from numerical solutions of these equations. As current in the circuit increasesl, magnetic field in the material increases, thus, the gap starts to shrink due to increased attractive force between gap and elastic restoring force in the material. With an appropriate selection of elastic constant of toroidal ferromagnetic material and design of gap structure it is possible to obtain the specified in both linear and nonlinear magnetic characteristics, such as current dependent and independent inductance.

• Journal of Sensor Science and Technology
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• v.25 no.5
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• pp.349-353
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• 2016

Recently, research on bolometer-type uncooled infrared image sensor which is made for industrial applications has been increasing. In general, it is difficult to calibrate fixed pattern noise (FPN) of bolometer array. In this paper, average-current calibration algorithm is presented for reducing bolometer resistance offset. A resistor which is produced by standard CMOS process, on the average, has a deviation. We compensate for deviation of each resistor using average-current calibration algorithm. The proposed algorithm has been implemented by a chip which is consisted of a bolometer pixel array, average current generators, current-to-voltage converters (IVCs), a digital-to-analog converter (DAC), and analog-to-digital converters (ADCs). These bolometer-resistor array and readout circuit were designed and manufactured by $0.35{\mu}m$ standard CMOS process.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.609-612
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• 2002

In this paper, a 12-bit 100-MHz CMOS current steering digital-to-analog converter is designed. In the D/A converter, a driver circuit using a dynamic latch is implemented to obtain low glitch and thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced stitching noise. And a threshold voltage-compensated current source. The D/A converter is designed with 0.35-$\mu m$ CMOS technology at 3.3 V power supply and simulated with HSPICE. The maximum power dissipation of the designed DAC is 143 mW.

• Journal of the Semiconductor & Display Technology
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• v.3 no.1
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• pp.1-7
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• 2004

In this paper, we have developed the DC parameters test system which inspects the properties of DC parameters for semiconductor products. The developed system is interfaced by IBM-PC. It is consisted of CPLD part, ADC(Analog-to-Digital Converter), DAC(Digital-to-Analog Converter), voltage/current source, variable resistor and measurement part. In the proposed system, we have designed the constant voltage source and the constant current source in a part. In the comparison of results, the results of the simulation are very similar to the ones of the implementation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.6
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• pp.2484-2490
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• 2012

This study reports on the development and performance verification of cell simulation boards of simulator and the embedded program for board control of the battery management system (BMS) of electric vehicle (EV) cars, which manages the next-generation automotive lithium-ion battery pack. Here, we have improved the speed of the simulator by using operational (OP) amplifier and transistors that were connected in series. In addition, using a digital analog converter (DAC) in each channel, we have improved the performance by channel-to-channel isolation (isolation) as compared to the traditional methods. Furthermore, by constructing a current-limiting protection circuit, one can be protected from disturbance and, by utilizing a precision shunt resistor for the current sensor, we have increased the precision of the current control. In order to verify the performance of the developed simulator, we have performed the experiment 10 times, with values ranging from 0.5 V to 5 V, and a voltage drop step of 0.5 V. Significance analysis of experimental data, and repeatability tests were performed, showing an average standard deviation of 0.001~0.004 V, indicating high repeatability and high statistical significance of the current method and system.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.2
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• pp.205-213
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• 2002

This paper deals with the implementation of three-phase VSI systems which can control the power regenerated from DC bus line to AC supply. The overall system consists of the line-to-line voltage and line current sensors, an actual power calculator using d-q transformation method, a complex power controller with PI control scheme, a gating signal generator for modified ｑ-conduction mode, a DPLL for frequency followup, and Power circuits. Control board is constructed by using a 32-bit DSP TMS32C32, two EFLDs , six ADCs, and a DAC. To verify the performance of the proposed system, we designed and constructed the propotype with the power rating of 5kVA at AC 220V. Experimental results show that the regenerated active power is well controlled to its command vague and the regenerated reactive power still remained at nearly zero through all operating modes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.21-26
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• 2005

An area efficient, low power switch-matrix semidigital FIR reconstruction filter for delta-sigma D/A converter is proposed. Filter coefficients are quantified to 7-bit and 7 current sources that correspond to each coefficient bit are used. The proposed semidigital FIR reconstruction filter is designed in a 0.25 um CMOS process and incorporates 1.5 mm$^{2}$ of active area and a power consumption is 3.8 mW at 2.5 V supply. The number of switching transistors is 1419 at 205 filter order. Simulation results show that the filter output has a dynamic range of 104 dB and 84 dB attenuation of out-of-band quantization noise.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.5
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• pp.223-228
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• 2018

In this paper the water sensor using a coaxial cavity resonator is designed and manufactured. The water sensor which can sense water drop linearly has been constructed with voltage controlled oscillator(VCO), coaxial cavity resonator, RF switch, RF detector, A/D converter, DAC and micro controller. The operating frequency range of the designed water sensor is from 2.5GHz to 3.2GHz and the input voltage and current source are 24[V/DC] and 1[A]. The designed sensor circuit includes VCO, RF switch, RF detector which varies the frequency characteristics of the devices in the high frequency of 3GHz. And so we should correct the error of the frequency characteristics of those devices in the sensor circuit. To do this, we make the reference path which switches the signals to the RF detector directly without sending it to the resonator. According to the result of simulation and measurement, we can see that there is 0-50MHz difference between simulated resonator frequency and manufactured resonator frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.85-90
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• 2013

In this paper, 6bit SAR ADC tolerant to ionizing radiation is presented. Radiation tolerance is achieved by using the Dummy Gate Assisted (DGA) MOSFET which was proposed to suppress the leakage current induced by ionizing radiation and its comparing sample is designed with the conventional MOSFET. The designed ADC consists of binary capacitor DAC, dynamic latch comparator, and digital logic and was fabricated using a standard 0.35um CMOS process. Irradiation was performed by Co-60 gamma ray. After the irradiation, ADC designed with the conventional MOSFET did not operate properly. On the contrary, ADC designed with the DGA MOSFET showed a little parametric degradation of which DNL was increased from 0.7LSB to 2.0LSB and INL was increased from 1.8LSB to 3.2LSB. In spite of its parametric degradation, analog to digital conversion in the ADC with DGA MOSFET was found to be possible.

• Journal of IKEEE
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• v.28 no.2
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• pp.234-238
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• 2024

This paper presents a study on the integration of 3D-stacked dual-tip RRAM with a CNN accelerator architecture, leveraging its low drive current characteristics and scalability in a 3D stacked configuration. The dual-tip structure is utilized in a parallel connection format in a synaptic array to implement multi-level capabilities. It is configured within a Network-on-chip style accelerator along with various hardware blocks such as DAC, ADC, buffers, registers, and shift & add circuits, and simulations were performed for the CNN accelerator. The quantization of synaptic weights and activation functions was assumed to be 16-bit. Simulation results of CNN operations through a parallel pipeline for this accelerator architecture achieved an operational efficiency of approximately 370 GOPs/W, with accuracy degradation due to quantization kept within 3%.