• 제목/요약/키워드: cryptographic hash

검색결과 87건 처리시간 0.029초

Interval Two-dimensional Hash Chains and Application to a DRM system

  • Jung, Chae-Duk;Shin, Weon;Hong, Young-Jin;Rhee, Kyung-Hyune
    • 한국멀티미디어학회논문지
    • /
    • 제10권12호
    • /
    • pp.1663-1670
    • /
    • 2007
  • One-way hash chains are important cryptographic primitives and have been used as building blocks of various cryptographic applications. Advantages of one-way hash chains are their simplicity and efficiency for generation based on low-powered processors with short time. However, a drawback of one-way hash chains is their difficulty of control to compute interval values of one-way hash chains. That is, when hash values in one-way hash chain are used as encryption keys, if one hash value is compromised, then the attacker can compute other encryption keys from the compromised hash value. Therefore, direct use of one-way hash chains as encryption keys is limited to many cryptographic applications, such as pay per view system and DRM system. In this paper, we propose a new concept which is called interval hash chain using a hash function. In particular, proposed hash chains are made for only computing interval hash values by using two different one-way hash chains. The proposed scheme can be applied to contents encryption scheme for grading and partially usable contents in DRM system.

  • PDF

PRaCto: Pseudo Random bit generator for Cryptographic application

  • Raza, Saiyma Fatima;Satpute, Vishal R
    • KSII Transactions on Internet and Information Systems (TIIS)
    • /
    • 제12권12호
    • /
    • pp.6161-6176
    • /
    • 2018
  • Pseudorandom numbers are useful in cryptographic operations for using as nonce, initial vector, secret key, etc. Security of the cryptosystem relies on the secret key parameters, so a good pseudorandom number is needed. In this paper, we have proposed a new approach for generation of pseudorandom number. This method uses the three dimensional combinational puzzle Rubik Cube for generation of random numbers. The number of possible combinations of the cube approximates to 43 quintillion. The large possible combination of the cube increases the complexity of brute force attack on the generator. The generator uses cryptographic hash function. Chaotic map is being employed for increasing random behavior. The pseudorandom sequence generated can be used for cryptographic applications. The generated sequences are tested for randomness using NIST Statistical Test Suite and other testing methods. The result of the tests and analysis proves that the generated sequences are random.

Practical (Second) Preimage Attacks on the TCS_SHA-3 Family of Cryptographic Hash Functions

  • Sekar, Gautham;Bhattacharya, Soumyadeep
    • Journal of Information Processing Systems
    • /
    • 제12권2호
    • /
    • pp.310-321
    • /
    • 2016
  • TCS_SHA-3 is a family of four cryptographic hash functions that are covered by a United States patent (US 2009/0262925). The digest sizes are 224, 256, 384 and 512 bits. The hash functions use bijective functions in place of the standard compression functions. In this paper we describe first and second preimage attacks on the full hash functions. The second preimage attack requires negligible time and the first preimage attack requires $O(2^{36})$ time. In addition to these attacks, we also present a negligible time second preimage attack on a strengthened variant of the TCS_SHA-3. All the attacks have negligible memory requirements. To the best of our knowledge, there is no prior cryptanalysis of any member of the TCS_SHA-3 family in the literature.

Security Properties of Domain Extenders for Cryptographic Hash Functions

  • Andreeva, Elena;Mennink, Bart;Preneel, Bart
    • Journal of Information Processing Systems
    • /
    • 제6권4호
    • /
    • pp.453-480
    • /
    • 2010
  • Cryptographic hash functions reduce inputs of arbitrary or very large length to a short string of fixed length. All hash function designs start from a compression function with fixed length inputs. The compression function itself is designed from scratch, or derived from a block cipher or a permutation. The most common procedure to extend the domain of a compression function in order to obtain a hash function is a simple linear iteration; however, some variants use multiple iterations or a tree structure that allows for parallelism. This paper presents a survey of 17 extenders in the literature. It considers the natural question whether these preserve the security properties of the compression function, and more in particular collision resistance, second preimage resistance, preimage resistance and the pseudo-random oracle property.

드론 네트워크 보안을 위한 해시표 대체 방식의 능동 방어 기법 (MTD (Moving Target Detection) with Preposition Hash Table for Security of Drone Network)

  • 임성민;이민우;임재성
    • 한국정보통신학회논문지
    • /
    • 제23권4호
    • /
    • pp.477-485
    • /
    • 2019
  • 드론 산업의 발달로 인해 드론 네트워크의 보안이 중요해졌다. 특히, 드론 네트워크의 무선통신 감청과 이로 인한 불법 드론 공격, 서비스 거부 공격에 대한 방어가 필요하다. 본 논문에서는 드론 네트워크의 보안성 향상을 위해 능동 방어를 위한 네트워크 MTD (Moving Target Defense) 기법을 적용하는 방안을 제안한다. 기존의 네트워크 MTD 기법을 드론 네트워크에 적용하게 되면, 드론 식별을 위한 해시값이 무선통신 중 노출될 위험이 있고, 일대다 군집형 드론 네트워크로의 적용이 제한된다. 본 논문에서는 해시값 노출에 따른 보안 위험을 감소하기 위해 해시표 사전 배치(PHT, Preposition Hash Table) 방식을 사용하고, 해시값을 별도의 카운터로 대체한다. 드론 네트워크 상에 해시값을 직접 전송하지 않기 때문에 해시값 생성시 사용된 키 값의 노출 위험이 감소되고, 결과적으로 동일한 키의 사용 시간을 연장하게 됨으로써 드론 네트워크의 보안성 향상에 기여할 수 있다. 또한, 비행 중 드론의 키 교환을 하지 않기 때문에 일대다 군집형 드론 네트워크로의 적용이 가능하다. 모의실험을 통해 드론 네트워크 공격시 키 사용량과 패킷 전송 성공률을 확인하여 제안방식이 드론 네트워크의 보안성 향상에 기여할 수 있음을 확인하였다.

Bitcoin Cryptocurrency: Its Cryptographic Weaknesses and Remedies

  • Anindya Kumar Biswas;Mou Dasgupta
    • Asia pacific journal of information systems
    • /
    • 제30권1호
    • /
    • pp.21-30
    • /
    • 2020
  • Bitcoin (BTC) is a type of cryptocurrency that supports transaction/payment of virtual money between BTC users without the presence of a central authority or any third party like bank. It uses some cryptographic techniques namely public- and private-keys, digital signature and cryptographic-hash functions, and they are used for making secure transactions and maintaining distributed public ledger called blockchain. In BTC system, each transaction signed by sender is broadcasted over the P2P (Peer-to-Peer) Bitcoin network and a set of such transactions collected over a period is hashed together with the previous block/other values to form a block known as candidate block, where the first block known as genesis-block was created independently. Before a candidate block to be the part of existing blockchain (chaining of blocks), a computation-intensive hard problem needs to be solved. A number of miners try to solve it and a winner earns some BTCs as inspiration. The miners have high computing and hardware resources, and they play key roles in BTC for blockchain formation. This paper mainly analyses the underlying cryptographic techniques, identifies some weaknesses and proposes their enhancements. For these, two modifications of BTC are suggested ― (i) All BTC users must use digital certificates for their authentication and (ii) Winning miner must give signature on the compressed data of a block for authentication of public blocks/blockchain.

FPGA Implementation of a Cryptographic Accelerator for IPSec authentications

  • Lee, Kwang-Youb;Kwak, Jae-Chang
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2002년도 ITC-CSCC -2
    • /
    • pp.948-950
    • /
    • 2002
  • IPSec authentication provides support for data integrity and authentication of IP packets. Authentication is based on the use of a message authentication code(MAC). Hash function algorithm is used to produce MAC , which is referred to HMAC. In this paper, we propose a cryptographic accelerator using FPGA implementations. The accelator consists of a hash function mechanism based on MD5 algorithm, and a public-key generator based on a Elliptiv Curve algorithm with small scale of circuits. The accelator provides a messsage authentification as well as a digital signature. Implementation results show the proposed cryptographic accelerator can be applied to IPSec authentications.

  • PDF

ARIA/AES 블록암호와 Whirlpool 해시함수를 지원하는 통합 크립토 프로세서 설계 (An Integrated Cryptographic Processor Supporting ARIA/AES Block Ciphers and Whirlpool Hash Function)

  • 김기쁨;신경욱
    • 전기전자학회논문지
    • /
    • 제22권1호
    • /
    • pp.38-45
    • /
    • 2018
  • ARIA, AES 블록암호와 Whirlpool 해시함수를 단일 하드웨어 구조로 통합하여 효율적으로 구현한 크립토 프로세서에 대해 기술한다. ARIA, AES, Whirlpool의 알고리듬 특성을 기반으로 치환계층과 확산계층의 하드웨어 자원이 공유되도록 설계를 최적화하였다. Whirlpool 해시의 라운드 변환과 라운드 키 확장을 위해 라운드 블록이 시분할 방식으로 동작하도록 설계하였으며, 이를 통해 하드웨어 경량화를 이루었다. ARIA-AES-Whirlpool 통합 크립토 프로세서는 Virtex5 FPGA에 구현하여 하드웨어 동작을 검증하였으며, $0.18{\mu}m$ CMOS 셀 라이브러리로 합성한 결과 68,531 GE로 구현되었다. 80 MHz 클록 주파수로 동작하는 경우에, ARIA, AES 블록암호는 각각 602~787 Mbps, 682~930 Mbps, 그리고 Whirpool 해시는 512 Mbps의 성능을 갖는 것으로 예측되었다.

재등록이 필요 없는 암호 해시체인 기반의 일회용 패스워드 인증기법 (One-Time Password Authentication Scheme Based on Cryptographic Hash Chain without Re-Registration)

  • 신동진;박창섭
    • 정보보호학회논문지
    • /
    • 제27권6호
    • /
    • pp.1251-1259
    • /
    • 2017
  • 고정된 패스워드 그리고 패스워드의 사전공유라는 단순 패스워드가 지니는 문제점을 해결하기 위해 해시체인 기반의 일회용 패스워드가 제안되었다. 루트 해시값을 사전에 등록시킨 후에 사용하기 때문에 고정된 패스워드의 문제점을 해결하였으나, 해시체인을 구성하는 해시값들이 소진된 이후에는 새로운 해시체인의 루트 값을 재등록 하는 단점을 가지고 있다. 재등록을 필요로 하지 않는 여러 유형의 해시체인 기반의 일회용 패스워드 기법들이 제안되었으나, 제약조건 및 효율성 측면에서 문제점들을 내포하고 있다. 본 논문에서는 재등록이 요구되지 않으면서 기존 제약조건을 만족하면서도 매 인증 시 각 2회의 암호해시함수만으로 일회용 패스워드를 생성하고 이를 검증하는 해시체인 기반의 일회용 패스워드 기법을 새로이 제안하고 기존 기법들과 보안요구사항 및 효율성 측면에서 비교 분석한다.

Design of Cryptographic Hardware Architecture for Mobile Computing

  • Kim, Moo-Seop;Kim, Young-Sae;Cho, Hyun-Sook
    • Journal of Information Processing Systems
    • /
    • 제5권4호
    • /
    • pp.187-196
    • /
    • 2009
  • This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.