• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2005년도 추계학술발표회 및 workshop
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• pp.126-126
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• 2005

• 마이크로전자및패키징학회지
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• 제27권3호
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• pp.55-60
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• 2020

최근 참단 반도체 패키징 기술은 고성능 SIP(system in packaging) 구조로 발전해 가고 있고, 이를 실현시키기 위해서 구리 대 구리 접합은 가장 핵심적인 기술로 대두되고 있다. 구리 대 구리 접합 기술은 아직 구리의 산화 특성과 고온 및 고압력 공정 조건, 등 해결해야 할 문제점들이 남아 있다. 본 연구에서는 아르곤과 질소를 이용한 2단계 플라즈마 공정을 이용한 저온 구리 접합 공정의 접합 계면 품질을 정량적 접합 강도 측정을 통하여 확인하였다. 2단계 플라즈마 공정은 구리 표면에 구리 질화막을 형성하여 저온 구리 접합을 가능하게 한다. 구리 접합 후 접합 강도 측정은 4점 굽힘 시험법과 전단 시험법으로 수행하였으며, 평균 접합 전단 강도는 30.40 MPa로 우수한 접합 강도를 보였다.

• 한국세라믹학회지
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• 제49권5호
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• pp.417-422
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• 2012

Copper nano particles have been considered as the materials for conductive ink due to its good thermal, electrical conductivity and low cost. However, copper nanoparticles oxidize easily, decreasing dispersion stability and electrical conductivity. Therefore, it is important to develop a method to minimize oxidation of copper nano particles to improve its dispersion stability property in copper nano ink. In this study, copper nano particles were coated with 1-Octanethiol VSAM(Vaporized Self Assembled Multilayers) to prevent oxidation and coated copper powders were dispersed in conductive ink successfully by studying its relationship of different chain length of solvents to 1-Octanethiol coating layer to fabricate nano ink. Various alcohol solvents, such as 1-Hexanol, 1-Octanol, and 1-Decanol were used. The coating layer was observed using FESEM and TEM. Furthermore, dispersion of copper nano particles in nano inks, was characterized using Turbiscan analyzer, viscometer, and contact angle measurement tool.

• Advances in materials Research
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• 제1권2호
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• pp.109-113
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• 2012

Electromigration-induced void evolutions in typical upper and lower layer dual-inlaid Copper (Cu) interconnect structures were simulated by applying a phenomenological model resorting to Monte Carlo based simulations, which considers redistribution of heterogeneously nucleated voids and/or pre-existing vacancy clusters at the Copper/dielectric cap interface during electromigration. The results indicate that this model can qualitatively explain the electromigration-induced void evolutions observations in many studies reported by several researchers heretofore. These findings warrant need to re-investigate technologically important electromigration mechanisms by developing rigorous models based on similar concepts.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.245-245
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• 2009

l-D nanostructured materials have much more attention because of their outstanding properties and wide applicability in device fabrication. Copper oxide(CuO) has been realized as a p-type metal oxide semiconductor with narrow band gap of 1.2 -1.5eV. Copper oxide nanostructures can be synthesized by various growth method such as oxidation reaction, thermal evaporation thermal decomposition, sol-gel. and Mostly CuO nanowire prepared on the Cu substrate such as Copper foil, grid, plate. In this study, CuO NWs were grown by thermal oxidation (at various temperatures in air (1 atm)) of Cu metal deposited on CuO (20nm)/$SiO_2$(250nm)/Si. A 20nm-thick CuO layer was used as an adhesion layer between Cu metal and $SiO_2$

• 한국응용과학기술학회지
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• 제31권2호
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• pp.176-182
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• 2014

Using alkali treatment solution, neutrality treatment solution and acid treatment solution, the surface corrosion layer of copper plates and bronze plates that have been artificially corroded using HCl, $H_2SO_4$ and $HNO_3$ solutions were removed. In the case of alkali treatment solution, only air oxidation in the form of black tenorite and white cuproous chloride remained without being removed. In the case of using a neutrality treatment solution, a anhydrous type layer of reddish brown cupric chloride remained without being removed, together with this black and white corrosion substance. In the case of using an acid treatment solution, this red corrosion substance also remained, but all of the oxide was removed on the surface of the specimen that was treated by alternatively using alkali treatment solution and acid treatment solution. In the case of this treatment solution with the order of alkali-acid, oxidation no longer proceeded only through the distilled water cleaning process after treatment, thereby showing that oxidation from the cleaning solution no longer proceeded.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1994년도 추계 학술발표 강연 및 논문 개요집
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• pp.51-52
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• 1994

• 한국재료학회지
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• 제22권7호
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• pp.335-341
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• 2012

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.

• Transactions on Electrical and Electronic Materials
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• 제8권4호
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• pp.174-177
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• 2007

We fabricated organic field-effect transistors (OFETs) based a fluorinated copper phthalocyanine ($F_{16}CuPC$) and copper phthalocyanine (CuPc) as an active layer. And we observed the surface morphology of the $F_{16}CuPC$ thin film. The $F_{16}CuPC$ thin film thickness was 40 nm, and the channel length was $50{\mu}m$, channel width was 3 mm. And we also fabricated the $F_{16}CuPc/CuPc$ double layer FET and with different $F_{16}CuPc$ film thickness devices. We observed the typical current-voltage (I-V) characteristics and capacitance-voltage (C-V) in $F_{16}CuPc$ FET and we calculated the effective mobility. From the double layer FET devices, we observed the higher drain current more than single layer FET devices.

• 한국전기화학회:학술대회논문집
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• 한국전기화학회 2005년도 수소연료전지공동심포지움 2005논문집
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• pp.383-390
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• 2005

Effect of applying a DC voltage on the interfacial reaction at the metal to zirconia interface was investigated utilizing an oxygen ionic conductivity of partially stabilized zirconia. The joining of copper rod and zirconia tube was carried out in Ar gas atmosphere at $1000^{\circ}C$. There are two type of the joining. The one is the reaction bond consisting of copper and zirconia was dominated by surface reaction with a undetectable very thin layer. It was found that copper elements were diffused to zirconia side, but that Zr ions were not diffused to copper side. These results mean application of a DC voltage to migrate oxygen to the copper-zirconia interface can oxidize metal at the copper-zirconia interface and the bonding reaction between zirconia and copper oxide may occur. The other is the reaction bonding was dominated by interdiffusion with a very thick interface layer. This result mean application of a DC voltage can reduce zirconia at the interface. The bonding reaction is to be an alloying between Zr and Cu.