• 한국전자통신학회논문지
• /
• 제17권1호
• /
• pp.173-180
• /
• 2022

근사 컴퓨팅은 효율적인 하드웨어 컴퓨팅 시스템을 설계하기 위한 유망한 방법이다. 근사 곱셈은 고성능, 저전력 컴퓨팅을 위한 근사 계산 방식에 사용되는 핵심적인 연산이다. 근사 4-2 compressor는 근사 곱셈을 위한 효율적인 하드웨어 회로를 구현할 수 있다. 본 논문에서는 저면적, 저전력 특성을 갖는 근사 곱셈기를 제안하였다. 근사 곱셈기 구조는 정확한 영역, 근사 영역, 상수 수정 영역의 세 영역으로 나누어진다. 새로운 4:2 근사 compressor를 사용하여 근사 영역의 부분 곱 축소를 단순화하고, 간단한 오류 수정 방식을 사용하여 근사로 인한 오류를 보상한다. 상수 수정 영역은 오차를 줄이기 위해 확률 분석을 통한 상수를 사용하였다. 8×8 곱셈기에 대한 실험 결과, 제안한 근사 곱셈기는 기존의 4-2 compressor 기반의 근사 곱셈기보다 적은 면적을 요구하면서 적은 전력을 소비함을 보였다.

• 소성∙가공
• /
• 제8권1호
• /
• pp.47-56
• /
• 1999

The governing functional in plastic deformation has to satisfy the incompressibility constraint. This incompressibility constraint imposed on velocity fields can be removed by introducing either Lagrange multiplier or the penalty constant into the functional. In this study, two-dimensional rigid plastic FEM programs using these schemes were developed. These two programs and DEFORM were applied in a cylinder upsetting and a closed die forging to compare the values of load, local mean stress and volume loss. As the results, the program using Lagrange multiplier obtained a more exact and stable solution, but it took more computational time than the program using the penalty constant. Therefore, according to user's need, one of these two programs can be chosen to simulate a metal forming processes.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제17권1호
• /
• pp.101-109
• /
• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

• 대한전자공학회논문지
• /
• 제2권2호
• /
• pp.9-16
• /
• 1965

The characteristics of electronic multipliers and their accuracy are analyzed. From the analysis a low cost, four-quadrant timedivision electronic multiplier jis built. This multiplier produces an output voltage equal to 0.01 of the instantaneous product of two input voltage representing independent variables. Each input may either be constant or vary with time over a range of ${\pm}$100 volts. Drift and noise in this multiplier are kept at very low level and dynamic response is below 0.5 decibels up to 700 cycles per second. Methods of testing this multiplier and the results are also described. It is shown that the results agree with theoretical values satisfactorily.

• 산업기술연구
• /
• 제27권B호
• /
• pp.245-253
• /
• 2007

Failure rate serves as a pivotal role in reliability study. Of all, the constant failure rate is the most popularly used in field exercises. In reality, however, the electrical and electronic parts' life is represented by not only the constant failure rate but the decreasing and/or increasing failure rates. Explicit consideration and incorporation of them into the model development may yield more desirable results. In this study, we built a reliability model for failure rates varying over time intervals and derived well known measures such as probability density function, reliability function, mean life, moments, and mission time. We then evaluated mean life with consideration of the first-year multiplier and compared the results those with constant failure rate. The results given in the study may provide a reference applying for practical decision making.

• 한국정보통신학회논문지
• /
• 제18권1호
• /
• pp.78-83
• /
• 2014

본 논문에서는 연산 시간이 긴 곱셈기 패스를 낮은 주파수에서 동작하는 저면적의 HEVC(High Efficiency Video Coding)용 다중 모드 일차원 변환 블록을 구현하는 효율적인 방법을 제시하였다. 제시한 방법은 전체 면적을 줄이기 위하여 일반적인 변수와 변수를 입력으로 받는 곱셈기 대신 행렬의 계수 특성을 이용한 상수와 변수를 입력으로 받는 상수 곱셈기를 사용하였다. 상수 곱셈기 사용으로 인하여 전체적인 처리량을 증가시켰으며 늘어난 처리량으로 인해 남는 동작 사이클을 이용하여 연산시간이 많이 걸리는 곱셈기 부분에 멀티 사이클 패스를 구성하여 곱셈기의 동작 주파수를 낮게 하면서 전체 연산량은 유지시켰다. TSMC 0.18um CMOS 공정 라이브러리를 이용하여 실제 하드웨어를 구현한 결과 4k($3840{\times}2160$) 영상을 기준으로 최소 동작 주파수는 186MHz이고 최대 동작 주파수는 300MHz이다.

• International Journal of Internet, Broadcasting and Communication
• /
• 제16권1호
• /
• pp.17-28
• /
• 2024

As listed as one of the most important requirements for Post-Quantum Cryptography standardization process by National Institute of Standards and Technology, the resistance to various side-channel attacks is considered very critical in deploying cryptosystems in practice. In fact, cryptosystems can easily be broken by side-channel attacks, even though they are considered to be secure in the mathematical point of view. The timing attack(TA) and the simple power analysis attack(SPA) are such side-channel attack methods which can reveal sensitive information by analyzing the timing behavior or the power consumption pattern of cryptographic operations. Thus, appropriate measures against such attacks must carefully be considered in the early stage of cryptosystem's implementation process. The Montgomery multiplier is a commonly used and classical gadget in implementing big-number-based cryptosystems including RSA and ECC. And, as recently proposed as an alternative of building blocks for implementing post quantum cryptography such as lattice-based cryptography, the big-number multiplier including the Montgomery multiplier still plays a role in modern cryptography. However, in spite of its effectiveness and wide-adoption, the multiplier is known to be vulnerable to TA and SPA. And this paper proposes a new countermeasure for the Montgomery multiplier against TA and SPA. Briefly speaking, the new measure first represents a multiplication operand without 0 digits, so the resulting multiplication operation behaves in a very regular manner. Also, the new algorithm removes the extra final reduction (which is intrinsic to the modular multiplication) to make the resulting multiplier more timing-independent. Consequently, the resulting multiplier operates in constant time so that it totally removes any TA and SPA vulnerabilities. Since the proposed method can process multi bits at a time, implementers can also trade-off the performance with the resource usage to get desirable implementation characteristics.

• 보건행정학회지
• /
• 제9권4호
• /
• pp.65-86
• /
• 1999

In this study, we investigate the welfare effect of mandatory prescription(MP) in Korea. An immediate effect of MP is the increase in the implicit price of prescribed medicine, which could be obtained easily from drug stores before MP. This will lower the quantity demanded. which will in turn reduce the abuse of drugs. The key to the cost-benefit analysis of MP, therefore, should be focused on this point; price increase in the cost side and quantity decrease in the benefit side. Since we do not have as much information as needed for the analysis, however, we made strong assumptions for the clarity of numbers; the severity of moral hazard of medical doctors related to the sales of hospital drugs, constant demand elasticity, constant benefit multiplier of reduced drug usage, and so on, With these rather strong assumptions, we find that i) the benefit side is much more sensitive to demand elasticity than the cost side effect ii) the larger the demand elasticity, the greater the size of net gain of MP, though the result depends on the size of the benefit multiplier. This analysis shows that we need to have more information on the specific institutional path of health benefit diffusion caused by the reduction of drug usage, which was the major target of MP.

• 대한수학회보
• /
• 제51권4호
• /
• pp.933-942
• /
• 2014

We give a representation of the component of solutions with characteristic multiplier 1 in a periodic linear inhomogeneous continuous system. It follows from this representation that asymptotic behaviors of the component of solutions to the system and to its associated homogeneous system are quite different, though they are similar in the case where the characteristic multiplier is not 1. Moreover, the representation is applicable to linear discrete systems with constant coefficients.

• 한국전자통신학회논문지
• /
• 제17권4호
• /
• pp.671-678
• /
• 2022

근사 컴퓨팅은 정확한 결과 대신에 허용 가능한 정도의 부정확한 결과를 도출하는 연산 기법이다. 근사 곱셈은 고성능, 저전력 컴퓨팅을 위한 근사 컴퓨팅 방식 중 하나이다. 본 논문에서는 근사 4-2 compressor와 향상된 전가산기를 사용하여 고집적·저전력·고속 근사 곱셈기를 제안하였다. 근사 4-2 compressor를 사용한 근사 곱셈기는 정확, 근사, 상수 수정 영역의 3개 영역으로 구성되어 있으며, 효율적인 부분 곱 감소 방식을 적용하여 각 영역의 크기를 조절하면서 성능을 비교하였다. 제안한 근사 곱셈기는 Verilog HDL로 설계하였고, 25nm CMOS 공정에서 Synopsys Design Compiler(DC)를 이용하여 면적, 전력, 지연시간을 분석하였으며, 기존의 근사 곱셈기에 비해 면적을 10.47%, 전력을 26.11%, 지연시간을 13% 줄였다.