• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.173-180
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• 2022

Approximate Computing is a promising method for designing hardware-efficient computing systems. Approximate multiplication is one of key operations used in approximate computing methods for high performance and low power computing. An approximate 4-2 compressor can implement hardware-efficient circuits for approximate multiplication. In this paper, we propose an approximate multiplier with low area and low power characteristics. The proposed approximate multiplier architecture is segmented into three portions; an exact region, an approximate region, and a constant correction region. Partial product reduction in the approximation region are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple error correction scheme. Constant correction region uses a constant calculated with probabilistic analysis for reducing error. Experimental results of 8×8 multiplier show that the proposed design requires less area, and consumes less power than conventional 4-2 compressor-based approximate multiplier.

• Transactions of Materials Processing
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• v.8 no.1
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• pp.47-56
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• 1999

The governing functional in plastic deformation has to satisfy the incompressibility constraint. This incompressibility constraint imposed on velocity fields can be removed by introducing either Lagrange multiplier or the penalty constant into the functional. In this study, two-dimensional rigid plastic FEM programs using these schemes were developed. These two programs and DEFORM were applied in a cylinder upsetting and a closed die forging to compare the values of load, local mean stress and volume loss. As the results, the program using Lagrange multiplier obtained a more exact and stable solution, but it took more computational time than the program using the penalty constant. Therefore, according to user's need, one of these two programs can be chosen to simulate a metal forming processes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.101-109
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• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

• Journal of the Korean Institute of Telematics and Electronics
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• v.2 no.2
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• pp.9-16
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• 1965

The characteristics of electronic multipliers and their accuracy are analyzed. From the analysis a low cost, four-quadrant timedivision electronic multiplier jis built. This multiplier produces an output voltage equal to 0.01 of the instantaneous product of two input voltage representing independent variables. Each input may either be constant or vary with time over a range of ${\pm}$100 volts. Drift and noise in this multiplier are kept at very low level and dynamic response is below 0.5 decibels up to 700 cycles per second. Methods of testing this multiplier and the results are also described. It is shown that the results agree with theoretical values satisfactorily.

• Journal of Industrial Technology
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• v.27 no.B
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• pp.245-253
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• 2007

Failure rate serves as a pivotal role in reliability study. Of all, the constant failure rate is the most popularly used in field exercises. In reality, however, the electrical and electronic parts' life is represented by not only the constant failure rate but the decreasing and/or increasing failure rates. Explicit consideration and incorporation of them into the model development may yield more desirable results. In this study, we built a reliability model for failure rates varying over time intervals and derived well known measures such as probability density function, reliability function, mean life, moments, and mission time. We then evaluated mean life with consideration of the first-year multiplier and compared the results those with constant failure rate. The results given in the study may provide a reference applying for practical decision making.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.78-83
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• 2014

This paper suggest an effective idea to implement an low area multi-mode one dimension transform block of HEVC(High Efficiency Video Coding). The time consuming multiplier path is designed to operate on low frequency. Normal multipliers dealing with variable operands are replaced with smaller constant multipliers which do the product with constant coefficient and variable only using shifters and adders. This scheme increases total multiplier counts but entire areas are reduced owing to smaller area of constant multiplier. Idle cycles caused by doubled multipliers enable to use multi-cycle paths on the cycle eating multiplier data path. Operating frequency is lowered by multi-cycle path but total throughput is maintained. This structure is implemented with TSMC 0.18 CMOS process library, and operated on 186MHz frequency to process a 4k($3840{\times}2160$) image. Max operating frequency is 300MHz.

• International Journal of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.17-28
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• 2024

As listed as one of the most important requirements for Post-Quantum Cryptography standardization process by National Institute of Standards and Technology, the resistance to various side-channel attacks is considered very critical in deploying cryptosystems in practice. In fact, cryptosystems can easily be broken by side-channel attacks, even though they are considered to be secure in the mathematical point of view. The timing attack(TA) and the simple power analysis attack(SPA) are such side-channel attack methods which can reveal sensitive information by analyzing the timing behavior or the power consumption pattern of cryptographic operations. Thus, appropriate measures against such attacks must carefully be considered in the early stage of cryptosystem's implementation process. The Montgomery multiplier is a commonly used and classical gadget in implementing big-number-based cryptosystems including RSA and ECC. And, as recently proposed as an alternative of building blocks for implementing post quantum cryptography such as lattice-based cryptography, the big-number multiplier including the Montgomery multiplier still plays a role in modern cryptography. However, in spite of its effectiveness and wide-adoption, the multiplier is known to be vulnerable to TA and SPA. And this paper proposes a new countermeasure for the Montgomery multiplier against TA and SPA. Briefly speaking, the new measure first represents a multiplication operand without 0 digits, so the resulting multiplication operation behaves in a very regular manner. Also, the new algorithm removes the extra final reduction (which is intrinsic to the modular multiplication) to make the resulting multiplier more timing-independent. Consequently, the resulting multiplier operates in constant time so that it totally removes any TA and SPA vulnerabilities. Since the proposed method can process multi bits at a time, implementers can also trade-off the performance with the resource usage to get desirable implementation characteristics.

• Health Policy and Management
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• v.9 no.4
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• pp.65-86
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• 1999

In this study, we investigate the welfare effect of mandatory prescription(MP) in Korea. An immediate effect of MP is the increase in the implicit price of prescribed medicine, which could be obtained easily from drug stores before MP. This will lower the quantity demanded. which will in turn reduce the abuse of drugs. The key to the cost-benefit analysis of MP, therefore, should be focused on this point; price increase in the cost side and quantity decrease in the benefit side. Since we do not have as much information as needed for the analysis, however, we made strong assumptions for the clarity of numbers; the severity of moral hazard of medical doctors related to the sales of hospital drugs, constant demand elasticity, constant benefit multiplier of reduced drug usage, and so on, With these rather strong assumptions, we find that i) the benefit side is much more sensitive to demand elasticity than the cost side effect ii) the larger the demand elasticity, the greater the size of net gain of MP, though the result depends on the size of the benefit multiplier. This analysis shows that we need to have more information on the specific institutional path of health benefit diffusion caused by the reduction of drug usage, which was the major target of MP.

• Bulletin of the Korean Mathematical Society
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• v.51 no.4
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• pp.933-942
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• 2014

We give a representation of the component of solutions with characteristic multiplier 1 in a periodic linear inhomogeneous continuous system. It follows from this representation that asymptotic behaviors of the component of solutions to the system and to its associated homogeneous system are quite different, though they are similar in the case where the characteristic multiplier is not 1. Moreover, the representation is applicable to linear discrete systems with constant coefficients.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.4
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• pp.671-678
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• 2022

Approximate computing is an computational technique that is acceptable degree of inaccurate results of accurate results. Approximate multiplication is one of the approximate computing methods for high-performance and low-power computing. In this paper, we propose a high-density, low-power, and high-speed approximate multiplier using approximate 4-2 compressor and improved full adder. The approximate multiplier with approximate 4-2 compressor consists of three regions of the exact, approximate and constant correction regions, and we compared them by adjusting the size of region by applying an efficient partial product reduction. The proposed approximate multiplier was designed with Verilog HDL and was analyzed for area, power and delay time using Synopsys Design Compiler (DC) on a 25nm CMOS process. As a result of the experiment, the proposed multiplier reduced area by 10.47%, power by 26.11%, and delay time by 13% compared to the conventional approximate multiplier.