• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.944-953
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• 1990

This paper describes design and implementation of a real-time high-precision vision system for an automation of SMT(surface mounting technology ). Also, a part inspection algorithm which calculates the position and direction of SMD(surface mounted device) accurately and performs the ruling using those information are presented, and a parallel processing technique for implementing those algorithms is also described. For a real-time implementation of iage acquisition and processing, several hardware modules, namely, multi-functional A/D-D/A board, frame memory board are developed. Particularly, a PE (processing element) board which employs the DSP56001 DSP (digital signal processor) is developed for the purpose of concurrent processing of part inspection algorithms. A stand-alone vision system is built by integration of the developed hardware modules and related softwares.

• Journal of the Korean Operations Research and Management Science Society
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• v.18 no.3
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• pp.13-34
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• 1993

By operating on many part of a software system concurrently, the parallel processing computers may provide several orders of magnitude more computing power than traditional serial computers. If the Lagrangean approximation procedure is applied to a large scale manufacturing problem which is decomposable into many subproblems, the procedure is a perfect candidate for parallel processing. By distributing Lagrangean subproblems for given multiplier to multiple processors, concurrently running processors and modifying Lagrangean multipliers at the end of each iteration of a subgradient method,a parallel processing of a Lagrangean approximation procedure may provide a significant speedup. This purpose of this research is to investigate the potential of the parallelized Lagrangean approximation procedure (PLAP) for certain combinational optimization problems in manufacturing systems. The framework of a Plap is proposed for some combinatorial manufacturing problems which are decomposable into well-structured subproblems. The synchronous PLAP for the multistage dynamic lot-sizing problem is implemented on a parallel computer Alliant FX/4 and its computational experience is reported as a promising application of vector-concurrent computing.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.634-638
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• 1990

In this paper, the architecture of a dataflow logic solving processor for programmable logic controller is proposed. As the proposed DFLSP (dataflow logic solving processor) is designed based on the dataflow architecture, it has inherently concurrent processing and data synchronization capabilities. The proposed DFLSP is adequate for high speed programmable logic controllers and gets rid of data synchronization problem in hardware level. The performance of the proposed DFLSP is analyzed using computer simulations and prototype hardware. With single processing element, the logic solving time is 144 usec per 1K steps of logic program and with eight processing elements, the logic solving time is 23 usec per 1K steps of logic program with reasonable assumptions.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.3-5
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• 2007

Many continuous queries are important to be process efficiently in a data stream environment. It is applied a query index technique that takes linear performance irrespective of the number and width of intervals for processing many continuous queries. Previous researches are not able to support the dynamic insertion and deletion to arrange intervals for constructing an index previously. It shows that the insertion and search performance is slowed by the number and width of interval inserted. Many intervals have to be inserted and searched linearly in a data stream environment. Therefore, we propose Hashed Multiple Lists in order to process continuous queries linearly. Proposed technique shows fast linear search performance. It can be utilized the systems applying a sensor network, and preprocessing technique of spatiotemporal data mining.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.8
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• pp.309-315
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• 1986

We proposed a preliminary Data Flow Machine Model(DNL1) operating on the basis of Node Label. In this model, all the PMs(Processing Modules) were synchronized with the content of LC(Level Counter) and were not implemented dy the processing cability on conditional nodes. This paper presents an architecture of a concurrent multiprocessor system which was developed from DNL1 with two additional types of memories, CF(Control Flag) and ETF (Enabled Token Flag). The CF memory holds the control condition flag ('1' or '0') to be referenced to when a node is fired and the ETF represents the firability of a certain node. Firable nodes are fetched to the PU(Processing Unit) and processed. This Data Flow system can be extended hierarchically by a network of simple modules. The principle working elements of the machine are a set of PMs, each of which performs the execution of the data flow procedures held in a local memory, NTM(Node Token Memory) within the PM.

• Journal of Information Processing Systems
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• v.7 no.1
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• pp.63-74
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• 2011

As a powerful and flexible processor, the Graphic Processing Unit (GPU) can offer a great faculty in solving many high-performance computing applications. Sweep3D, which simulates a single group time-independent discrete ordinates (Sn) neutron transport deterministically on 3D Cartesian geometry space, represents the key part of a real ASCI application. The wavefront process for parallel computation in Sweep3D limits the concurrent threads on the GPU. In this paper, we present multi-dimensional optimization methods for Sweep3D, which can be efficiently implemented on the finegrained parallel architecture of the GPU. Our results show that the overall performance of Sweep3D on the CPU-GPU hybrid platform can be improved up to 4.38 times as compared to the CPU-based implementation.

• The Transactions of the Korea Information Processing Society
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• v.3 no.6
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• pp.1386-1396
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• 1996

In the distributed multimedia application, high throughput and low delay is one of the most important QoS(Quality of Service) requirement. Emerging high speed communication offers transmission rate above Gbps, but it can not be utilized efficiently by the performance bottlenecks of communication protocols. To overcom the problem, we propose a horizontal processing architecture that processes data as soon as it arrive from the network. Unfortunately, the OSI protocol stack often imposes ordering constraints that prevent concurrent processing of the protocol layers. By using a fixed packet format, the network layer through the presentation layer are processed in parallel. Our prototype shows that the proposed model has performance improvement up to 61% more advantage than the conventional approach.

• Journal of the Korea Society for Simulation
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• v.27 no.2
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• pp.61-69
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• 2018

As the technology of information and communication has developed over recent years, an embedded system is applied in multiple industries and becomes more complicated. For this reason, embedded system development cost and time are also increased. For decreasing the cost and time, this paper suggests requirement evaluation method for concurrent development of an embedded system based on Discrete Event System(DEVS) Formalism. This paper proposes a method of describing the requirements specification in the form of DEVS atomic model. Also, the paper proposes the evaluator model that compares evaluation target system and the requirements model that is an implementation of requirement specification and proposes the evaluation method using them. In addition, we propose a method to utilize the requirement model created for requirements evaluation in the concurrent development process of the embedded system. As the case study, this paper proceeds requirement evaluation of Kinect depth data processing system.

• The Journal of Korean Academy of Sensory Integration
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• v.21 no.3
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• pp.27-38
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• 2023

Objective : This study aims to verify the validity and reliability of the Korean version of the Sensory Processing and Self-Regulation Checklist (SPSRC) for children with and without autism spectrum disorder. Methods : The Pearson product-moment correlation coefficient was calculated using Short Sensory Profile (SSP) to verify concurrent validity. Construct validity was verified by comparing the sensory processing ability and self-regulation ability of the two groups. Cronbach's α was calculated in the case of internal consistency for reliability verification, and the test-retest reliability was verified through the Pearson correlation coefficient. Results : Based on the verification of the concurrent validity, the Korean version of SPSRC and SSP showed a statistically significant correlation (p < 0.01). The construct validity was found to have a statistically significant difference between the two groups in the area and sub-items of the Korean version of SPSRC (p < 0.001). For the internal consistency, Cronbach's α ranged from 0.700 to 0.975. The test-retest reliability showed that the correlation coefficient ranged from 0.937 to 0.997. Conclusion : The Korean version of SPSRC was confirmed to be an evaluation tool with high validity and reliability. It is expected to be used as an evaluation tool for planning treatment goals in clinical trials and as a meaningful basis for future research.

• Transactions of Materials Processing
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• v.26 no.3
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• pp.174-180
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• 2017

In this study, a new spot welding with electric resistance heated dies is suggested for the spot welding of non-ferrous metal plates for drawing and concurrent spot welding. This welding method involves two heating processes such as heating by conduction of electric resistance heated dies and heating by resistance between contacted surfaces of two plates by welding current induced to copper dies for the fusion of contacted metal. This welding process has welding variables such as current induced in heated and copper dies, the inner diameters of heated dies, and edge shape of the copper dies. Experimental conditions for each current should be established to get successful welding strength. The welding strength could reach to the desired value in industrial fields under the following conditions of contact diameters of heated dies in this case of overlapped aluminum5052 plates with 0.3-mm thickness: inner and outer diameters of 5.0 and 16mm, respectively; diameter of copper dies, 5.0mm; heating current, 6.8kA in heated steel dies; welding current, 8.6 kA in copper dies.