• The Pure and Applied Mathematics
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• v.30 no.3
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• pp.337-345
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• 2023

Different versions of the boundary Schwarz lemma for the 𝒩 (𝜌) class are discussed in this study. Also, for the function g(z) = z+b₂z²+b₃z³+... defined in the unit disc D such that g ∈ 𝒩 (𝜌), we estimate a modulus of the angular derivative of g(z) function at the boundary point 1 ∈ 𝜕D with g'(1) = 1 + 𝜎 (1 - 𝜌), where ${\rho}={\frac{1}{n}}{\sum\limits_{i=1}^{n}}g(c_i)={\frac{g^{\prime}(c_1)+g^{\prime}(c_2)+{\ldots}+g^{\prime}(c_n)}{n}}{\in}g^{\prime}(D)$ and 𝜌≠1, 𝜎 > 1 and c₁, c₂, ..., c_n ∈ 𝜕D. That is, we shall give an estimate below |g"(1)| according to the first nonzero Taylor coefficient of about two zeros, namely z = 0 and z ≠ 0. Estimating is made by using the arithmetic average of n different derivatives g'(c₁), g'(c₂), ..., g'(c_n).

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.502-504
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• 2010

We propose novel transition rule of cellular automata for image enhancement and sharpening algorithm using it. Transition rule present sequential and parallel behavior. it also satisfy Lyapunov function. This image sharpening was developed and experimented by using a dynamic feature of convergence to fixed points. We can obtain efficiently sharpened image by performing arithmetic operation at the gradual parts of difference of brightness without image information.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.340-344
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• 1986

This paper shows that we can design a vector-coordinate rotation processor and obtain the approximate evaluations of sine and cosine based upon the use of residue number systems. The algorithm results in the considerable improvement of the computation speed when compared to CORDIC algorithm. The results from computer simulation show that the mean error of sine and cosine is 0.0025 and the mean error of coordinate rotation arithmatic is 0.65. Also, the proposed processor has the efficiency for the design and fabrication of integrated circuit, because it consists of the array of idecntially structured look-up tables.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.409-414
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• 1986

To eliminate the requirement of multiplications in nonrecursive filter realization, the use of a delta modulation(DM) has been studied by several researchers. However, the structure of DM filters inevitably contains an intergrator that is cascaded with the arithmetic unit to operate convolution summation. In this paper we porpose a method to determine the coefficients that may be used for implementation of a DM filter without an integrator. Also, we obtain the condition by which one can exclude the response errors due to the elimination of the integrator. By computer simulations it is shown that the performance of the proposed filter is very good, providing that the condition is satisfied.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.24-33
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• 2006

The effective geometry processing IP architecture for mobile SoC that has real time 3D graphics acceleration performance in mobile information system is proposed. Base on the proposed IP architecture, we design the floating point arithmetic unit needed in geometry process and the floating point geometry processor supporting the 3D graphic international standard OpenGL-ES. The geometry processor is implemented by 160k gate area in a Xilinx-Vertex FPGA and we measure the performance of geometry processor using the actual 3D graphic data at 80MHz frequency environment The experiment result shows 1.5M polygons/sec processing performance. The power consumption is measured to 83.6mW at Hynix 0.25um CMOS@50MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.64-71
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• 2014

Multiplier performs a complex arithmetic operation in various signal processing algorithms such as multimedia and communication system. The multiplier also suffers from its relatively large signal propagation delay, high power dissipation, and large area requirement. This paper presents memristor-CMOS based reconfigurable multiplier reducing area occupation of the multiplier circuitry and increasing compatibility using optimized bit-width for various applications. The performance of the memristor-CMOS based reconfigurable multiplier are estimated with memristor SPICE model and 180 nm CMOS process under 1.8 V supply voltage. The circuit shows performance improvement of 61% for area, 38% for delay and 28% for power consumption respectively compared with the conventional reconfigurable multipliers. It also has an advantage for area reduction of 22% against a twin-precision multiplier.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.23-30
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• 2006

This paper presents design andd verification of a circuit that improves the control-operation problems of Stored Program Optical Computer (SPOC), which is an optical computer using $LiNbO_3$ optical switching element. Since the memory of SPOC takes the Delay Line Memory (DLM) architecture and instructions that are needless of operands should go though memory access stages, SPOC memory have problems; it takes immoderate access time and unnecessary operations are executed in Arithmetic Logical Unit (ALU) because desired operations can't be selectively executed. In this paper, improvement on circuit has been achieved by removing the memory access of instructions that are needless of operands by decoding instructions before locating operand. Unnecessary operations have been reduced by sending operands to some specific operational units, not to all the operational units in ALD. We show that total execution time of a program is minimized by using the Dual Instruction Register(DIR) architecture.

• Journal of the Korean School Mathematics Society
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• v.2 no.1
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• pp.67-77
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• 1999

The purpose of this study was to design models of CAI programs for the graphing of quadratic functions. In order to achieve this aim, I researched the relationship between mathematics educations computer programing, and theoretical approaches of CAI. The CAI program, which was developed based on my research was then positively applied to the mathematics education class in a middle school. First of all, I selected two classes -An experimental class and a comparative class. The experimental class was taught using the CAI program and the comparative class was taught by conventional methods of instruction. The results of this study are as follows: 1. The class taught by using the CAI program scored higher academic achievement than the class taught by conventional methods of instruction. 2. The analysis of the two classes' academic scores shows that the instruction using CAI program is more effective than that by conventional methods in improving students' academic achievement. The followings are suggestion for developing CAI programs and students' understanding through this study. 1. Non computer specialists will require a few months to develope an effect CAI program. Thus, development of easier, more clearly defined and flexible models must be constructed. 2. Teachers should be eager to use pre-existing models to motivate their students irregardless of their own development of programs. 3. School should provide computer rooms with a perfect net work in proportion to class size. 4. CAI programs can make students understand faster and more directly than blackboard examples. However, inconsideration of mathematical characteristics, arithmetic by hand is more effective for the students' memory retention. Computers is an effective tool of instruction. But it is most effective when used in conjunction with other methods that complement its use.

• Journal of KIISE:Software and Applications
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• v.27 no.1
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• pp.24-32
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• 2000

BCI(Brain-Computer Interface) is studied to control the machines with brain. In this study, an EEG(Electroencephalography) signal classification model is proposed. The model gets EEG pattern from each subject's brain and extracts characteristic features. The model discriminates the EEG patterns by using those extracted characteristic features of each subject. The proposed method classifies each pair of the given tasks and combines the results to give the final result. Four tasks such as rest, movement, mental-arithmetic calculation and point-fixing were used in the experiment. Over 90% of the trials, the model yielded successful results. The model exploits characteristic features of the subjects and the weight table that was produced after training. The analysis results of the model such as its high success rates and short processing time show that it can be used in a real-time brain-computer interface system.

• Journal of the Korea Society of Computer and Information
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• v.29 no.6
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• pp.89-100
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• 2024

The primary goal of software testing is to identify and correct errors within software. A key challenge in this process is error masking, where errors disappear internally before reaching the output. This paper investigates the causes and characteristics of error masking, which complicates software testing. The study involved injecting artificial errors into three software programs to examine the extent of error masking by various test cases and to explore the underlying reasons. The experiment yielded four major findings. First, about 50% of the error masking occurred because the errors were not executed. Second, among various operators, logical and arithmetic operators masked errors less frequently, while relational and temporal operators tended to mask errors more extensively. Third, certain test cases demonstrated exceptional effectiveness in propagating errors to the output. Fourth, the type of error injected influenced the masking effect.