• Title/Summary/Keyword: computation complexity

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URBAN COMPLEXITY ESTIMATION INDICES BASED ON 3D DISCRETE WAVELET TRANSFORM OF REMOTELY SENSED IMAGERY;THE PRELIMINARY INTERPRETATION WITH LAND COVER MAP

  • Yoo, Hee-Young;Lee, Ki-Won;Kwon, Byung-Doo
    • Proceedings of the KSRS Conference
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    • 2007.10a
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    • pp.405-409
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    • 2007
  • Each class in remotely sensed imagery has different spectral and spatial characteristics. Natural features have relatively smaller spatial changes than spectral changes. Meanwhile, urban area in which buildings, roads, and cars are included is inclined to face more changes of spatial variation than spectral one. This study aims to propose the new urban complexity index (UCI) based on the 3D DWT computation of remotely sensed imageries considering these characteristics. And then we analyze relation between index and land cover map. The 3DWUCI values are related to class and the indices of urban area are greater than natural area. The proposed UCI could be used to express effectively the standard of urban complexity over a wide area.

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Nulling algorithm design using approximated gradient method (근사화된 Gradient 방법을 사용한 널링 알고리즘 설계)

  • Shin, Chang Eui;Choi, Seung Won
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.9 no.1
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    • pp.95-102
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    • 2013
  • This paper covers nulling algorithm. In this algorithm, we assume that nulling points are already known. In general, nulling algorithm using matrix equation was utilized. But, this algorithm is pointed out that computational complexity is disadvantage. So, we choose gradient method to reduce the computational complexity. In order to further reduce the computational complexity, we propose approximate gradient method using characteristic of trigonometric functions. The proposed method has same performance compared with conventional method while having half the amount of computation when the number of antenna and nulling point are 20 and 1, respectively. In addition, we could virtually eliminate the trigonometric functions arithmetic. Trigonometric functions arithmetic cause a big problem in actual implementation like FPGA processor(Field Programmable gate array). By utilizing the above algorithm in a multi-cell environment, beamforming gain can be obtained and interference can be reduced at same time. By the above results, the algorithm can show excellent performance in the cell boundary.

Improved Method for the Macroblock-Level Deblocking Scheme

  • Le, Thanh Ha;Jung, Seung-Won;Baek, Seung-Jin;Ko, Sung-Jea
    • ETRI Journal
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    • v.33 no.2
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    • pp.194-200
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    • 2011
  • This paper presents a deblocking method for video compression in which the blocking artifacts are effectively extracted and eliminated based on both spatial and frequency domain operations. Firstly, we use a probabilistic approach to analyze the performance of the conventional macroblock-level deblocking scheme. Then, based on the results of the analysis, an algorithm to reduce the computational complexity is introduced. Experimental results show that the proposed algorithm outperforms the conventional video coding methods in terms of computation complexity while coding efficiency is maintained.

Low Complexity Systolic Montgomery Multiplication over Finite Fields GF(2m) (유한체상의 낮은 복잡도를 갖는 시스톨릭 몽고메리 곱셈)

  • Lee, Keonjik
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.18 no.1
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    • pp.1-9
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    • 2022
  • Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

Match Field based Algorithm Selection Approach in Hybrid SDN and PCE Based Optical Networks

  • Selvaraj, P.;Nagarajan, V.
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.12
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    • pp.5723-5743
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    • 2018
  • The evolving internet-based services demand high-speed data transmission in conjunction with scalability. The next generation optical network has to exploit artificial intelligence and cognitive techniques to cope with the emerging requirements. This work proposes a novel way to solve the dynamic provisioning problem in optical network. The provisioning in optical network involves the computation of routes and the reservation of wavelenghs (Routing and Wavelength assignment-RWA). This is an extensively studied multi-objective optimization problem and its complexity is known to be NP-Complete. As the exact algorithms incurs more running time, the heuristic based approaches have been widely preferred to solve this problem. Recently the software-defined networking has impacted the way the optical pipes are configured and monitored. This work proposes the dynamic selection of path computation algorithms in response to the changing service requirements and network scenarios. A software-defined controller mechanism with a novel packet matching feature was proposed to dynamically match the traffic demands with the appropriate algorithm. A software-defined controller with Path Computation Element-PCE was created in the ONOS tool. A simulation study was performed with the case study of dynamic path establishment in ONOS-Open Network Operating System based software defined controller environment. A java based NOX controller was configured with a parent path computation element. The child path computation elements were configured with different path computation algorithms under the control of the parent path computation element. The use case of dynamic bulk path creation was considered. The algorithm selection method is compared with the existing single algorithm based method and the results are analyzed.

A New Adaptive Controller Compensating Nonlinear Distortions of a Speaker (스피커의 비선형 왜곡을 보정하는 새로운 적응 제어기)

  • Kwon, Oh-Sang
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.10
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    • pp.1087-1094
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    • 2014
  • In general, a speaker generates nonlinear distortions owing to a design principle, manufacturing process, and so on, which decreases and changes a sound quality. So, if the speaker is linearized by compensating these nonlinear distortions, the sound quality and satisfaction can be increased. In this paper, a new adaptive controller was proposed to be applied for compensating nonlinear distortions of a speaker. Through computer simulations as well as the analytical analysis, it could be shown that it is possible for both conventional adaptive controller and proposed adaptive controller, to be applied for linearizing the speaker with nonlinear distortions. Also, the simulations results demonstrated that the proposed adaptive controller may have faster convergence speed and better capability of compensating the nonlinear distortion than the conventional adaptive controller with nearly equal computation complexity.

A Non-parametric Fast Block Size Decision Algorithm for H.264/AVC Intra Prediction

  • Kim, Young-Ju
    • Journal of information and communication convergence engineering
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    • v.7 no.2
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    • pp.193-198
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    • 2009
  • The H.264/ AVC video coding standard supports the intra prediction with various block sizes for luma component and a 8x8 block size for chroma components. This new feature of H.264/AVC offers a considerably higher improvement in coding efficiency compared to previous compression standards. In order to achieve this, H.264/AVC uses the Rate-distortion optimization (RDO) technique to select the best intra prediction mode for each block size, and it brings about the drastic increase of the computation complexity of H.264 encoder. In this paper, a fast block size decision algorithm is proposed to reduce the computation complexity of the intra prediction in H.264/AVC. The proposed algorithm computes the smoothness based on AC and DC coefficient energy for macroblocks and compares with the nonparametric criteria which is determined by considering information on neighbor blocks already reconstructed, so that deciding the best probable block size for the intra prediction. Also, the use of non-parametric criteria makes the performance of intra-coding not be dependent on types of video sequences. The experimental results show that the proposed algorithm is able to reduce up to 30% of the whole encoding time with a negligible loss in PSNR and bitrates and provides the stable performance regardless types of video sequences.

Efficient Hardware Implementation of Real-time Rectification using Adaptively Compressed LUT

  • Kim, Jong-hak;Kim, Jae-gon;Oh, Jung-kyun;Kang, Seong-muk;Cho, Jun-Dong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.1
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    • pp.44-57
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    • 2016
  • Rectification is used as a preprocessing to reduce the computation complexity of disparity estimation. However, rectification also requires a complex computation. To minimize the computing complexity, rectification using a lookup-table (R-LUT) has been introduced. However, since, the R-LUT consumes large amount of memory, rectification with compressed LUT (R-CLUT) has been introduced. However, the more we reduce the memory consumption, the more we need decoding overhead. Therefore, we need to attain an acceptable trade-off between the size of LUT and decoding overhead. In this paper, we present such a trade-off by adaptively combining simple coding methods, such as differential coding, modified run-length coding (MRLE), and Huffman coding. Differential coding is applied to transform coordinate data into a differential form in order to further improve the coding efficiency along with Huffman coding for better stability and MRLE for better performance. Our experimental results verified that our coding scheme yields high performance with maintaining robustness. Our method showed about ranging from 1 % to 16 % lower average inverse of compression ratio than the existing methods. Moreover, we maintained low latency with tolerable hardware overhead for real-time implementation.

Multiplexer-Based Finite Field Multiplier Using Redundant Basis (여분 기저를 이용한 멀티플렉서 기반의 유한체 곱셈기)

  • Kim, Kee-Won
    • IEMEK Journal of Embedded Systems and Applications
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    • v.14 no.6
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    • pp.313-319
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    • 2019
  • Finite field operations have played an important role in error correcting codes and cryptosystems. Recently, the necessity of efficient computation processing is increasing for security in cyber physics systems. Therefore, efficient implementation of finite field arithmetics is more urgently needed. These operations include addition, multiplication, division and inversion. Addition is very simple and can be implemented with XOR operation. The others are somewhat more complicated than addition. Among these operations, multiplication is the most important, since time-consuming operations, such as exponentiation, division, and computing multiplicative inverse, can be performed through iterative multiplications. In this paper, we propose a multiplexer based parallel computation algorithm that performs Montgomery multiplication over finite field using redundant basis. Then we propose an efficient multiplexer based semi-systolic multiplier over finite field using redundant basis. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the AT complexity of the proposed multiplier is improved by approximately 19% and 65% compared to the multipliers of Kim-Han and Choi-Lee, respectively. Therefore, our multiplier is suitable for VLSI implementation and can be easily applied as the basic building block for various applications.

Image Interpolation Using Iterative Error Elimination (반복적 오차 제거를 이용한 영상 보간법)

  • Kim, Won-Hee;Piao, Fengji;Kim, Jong-Nam;Moon, Kwang-Seok
    • Journal of Korea Multimedia Society
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    • v.14 no.8
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    • pp.1000-1009
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    • 2011
  • Image interpolation is a technique which estimates the non-allocated pixel values on image scale-transform. It requires minimum computational complexity and minimum image quality degradation on the interpolated resultant images. In this paper we propose an image interpolation method using iterative error estimation. The proposed method consists of the following five steps: loss-information computational step, loss-information estimation step, loss-information application step, error computation step, and error application step. The experimental results obtained show that the average PSNR is increased by 3.3dB, subjective image quality is enhanced and the minimum computation complexity is decreased by 83%. The proposed image interpolation algorithm may be helpful in various applications such as image reconstruction and enlargement.