• Journal of radiological science and technology
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• v.33 no.3
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• pp.173-178
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• 2010

In projection radiography, two types of digital imaging systems are currently available, computed radiography (CR) and digital radiography (DR): a difference between them can be stated in terms of dose and image quality. In the Department of Radiology our hospital, a flat-panel DR equipment (Digital diagnost, Philips) and two CR systems (ADC Compact plus digitizer, AGFA) are employed. Eight standard radiographic examinations (Skull AP, Skull LAT, Chest PA, Chest LAT, Abdomen AP, L-spine AP, L-spine LAT, Pelvis AP) were considered: doses delivered to patients in terms of both entrance skin dose (ESD) were calculated and compared in order to study the dosimetric discrepancies between CR and DR. Assessment of image quality is undertaken by Consultant Radiologists to ensure that the quality criteria for diagnostic radiographic images of the European guidelines were met. Results showed that both ESD in DR are lower than that in CR; all images met the criteria in the European Guidelines for both modalities and were used for reporting by the radiologists. Since the operators are the same and the image quality is comparable in both modalities, this study shows that in the considered examinations, DR can perform better than CR from a dosimetric point of view.

• Journal of the Korean Society of Safety
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• v.29 no.1
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• pp.47-53
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• 2014

The application of advanced Main Control Room(MCR) is accompanied with lots of changes and different forms and features through the virtue of new digital technologies. The characteristics of these digital technologies and devices give many opportunities to the interface management, and can be integrated into a compact single workstation in advanced MCR so that workers can operate the plant with minimum physical burden under any operation conditions. However, these devices may introduce new types of human errors and thus a means to evaluate and prevent such errors is needed, especially those related to characteristics of digital devices. This paper reviewed the new type of human error hazards of tasks based on digital devices and surveyed researches on physiological assessment related to human error. An experiment was performed to verify human error hazards by physiological responses such as EEG which was measured to evaluate the cognitive workload of operators. And also, the performances of four tasks which are representative in human error hazard tasks based on digital devices were compared. Response time, ${\beta}$ power spectrum rate of each task by EEG, and mental workload by NASA-TLX were evaluated. In the results of the experiment, the rate of the ${\beta}$ power was increased in the task 1 and task 4 which are searching and navigating task and memory task of hierarchical information, respectively. In case of the mental workload, in most of evaluation items, task 1 and 4 were highly rated comparatively. In this paper, human error hazards might be identified by highly cognitive workload. Conclusively, it was concluded that the predictive method which is utilized in this paper and an experimental verification can be used to ensure the safety when applying the digital devices in Nuclear Power Plants (NPPs).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.355-366
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• 2022

This paper proposes a microcode-based neural network accelerator controller for artificial intelligence accelerators that can be reconstructed using a programmable architecture and provide the advantages of low-power and ultra-small chip size. In order for the target accelerator to support various neural network models, the neural network model can be converted into microcode through microcode compiler and mounted on accelerator to control the operators of the accelerator such as datapath and memory access. While the proposed controller and accelerator can run various CNN models, in this paper, we tested them using the YOLOv2-Tiny CNN model. Using a system clock of 200 MHz, the Controller and accelerator achieved an inference time of 137.9 ms/image for VOC 2012 dataset to detect object, 99.5ms/image for mask detection dataset to detect wearing mask. When implementing an accelerator equipped with the proposed controller as a silicon chip, the gate count is 618,388, which corresponds to 65.5% reduction in chip area compared with an accelerator employing a CPU-based controller (RISC-V).

• 재활복지
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• v.20 no.4
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• pp.31-54
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• 2016

The purpose of this study is to explore the improvement method of the emergency safety system as a social protection scheme for the elderly living alone with severe disabilities. The study was conducted by randomly choosing three regions in the metropolitan area (Jongno-gu, Seoul), the small-medium city (Yongin-si, Gyeonggi-do) and the rural area (Geochang-gun, Gyeongsangnam-do) among 17 cities and counties nationwide. The study method is based on the interview form of the structured questionnaires with city officials, county officials, and center operators. According to the results of the interview analysis, it was recognized that there was a need for an emergency safety system for the elderly living alone with severe disabilities. In spite of this necessity, there were problems about publicity for the discovery of victims of the blind spot in welfare, about inconvenience due to frequent malfunctions of the emergency equipment, about insufficient awareness of the security of the emergency officials and about supply and demand of manpower for 24-hour monitoring service. In order to improve the effective operation of the emergency safety system, it was the most urgent issue to formulate the legislation for responding to the crisis management of the vulnerable. A suggestion of this study is to build a safety system in which one-stop service is provided for the realization of compact welfare through the establishment of a MOU for linkage with community organizations, the full inspection of emergency equipment to solve safety equipment malfunction problems and the manpower supplement for 24-hour monitoring.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.