• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.3
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• pp.171-178
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• 2008

Pressure control of hydraulic pump using SRM with pressure predictor and direct torque control method is presented in this paper. Nowadays, high efficiency and high performance motor drive is much interested in hydraulic pump system. But the hydraulic pump system has an inherent defect that its dynamic behavior causes by interaction between the sensor and hydraulic load. It will make low performance of whole system, even unstable and oscillatory. Proposed system integrates pressure predictor and direct instantaneous torque control (DITC). The pressure predictor includes Smith predictor, which is easy to improve unstable or long oscillation in traditional negative feedback control and popular PID control architectures. And DITC method can reduce inherent torque ripple of SRM, and develop smooth torque to load, which can increase stability and improve the torque response of SR drive. So high dynamic performance and stabilization can achieved proposed hydraulic system. At last, the proposed hydraulic system is verified by simulation and experimental results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.39-44
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• 2003

As the portable electronic equipments are developed and popularized, the batteies are more important. To prolong life of the equipments, engineers demand to have batteries of high-power density and they are used to use Li-ion batteries popularly Li-ion batteries are better than conventional batteries, Ni-cd, about power density per volume and weight, but they have a fault that discharge voltage of them goes down. In order to maximize life of the Li-ion batterries, we have to use a converter which is suitable for the characteristic of Li-ion batteries. Therefore, capacitive idling SEPIC(Single Ended Primary Inductance Converter) that is derived from the SEPIC topology is proposed as a source of the Portable low-power applications. The converter has characteristics of buck-boost porformance. Besides, that makes it possible to increase the switching frequency by partial soft commutation of power switches through adding a diode and a switch. This paper is presented the characteristics, DC voltage conversion ratio, circuits of operation modes, of the converter and it is analized and implemented.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.10
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• pp.910-916
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• 2015

A sensorless motor control scheme with conventional back-Electro Motive Force (EMF) sensing based on zero crossing point (ZCP) detection has been widely used in various applications. However, there are several problems with the conventional method for effectively driving sensorless brushless motors. For example, a phase mismatch of 30 degrees occurs between the ZCP and commutation time. Additionally, most of the motor speed/current controls are achieved based on a pulse width modulation (PWM) method, which generates significant noise that distracts the back-EMF sensing. Due to the PWM switching, the ZCP is not deterministic, and thus the efficiency of the motor is reduced because the phase transition points become uncertain. Moreover, the motor driving performance is degraded at a low speed range due to the effect of PWM noise. To solve these problems, an improved back-EMF detection method based on a differential line method is proposed in this paper. In addition, the proposed sensorless BLDC driver addresses the problems by using a variable voltage driver generated from a buck converter. The variable voltage driver does not generate the PWM switching noise. Consequently, the proposed sensorless motor driver improves 1) the signal-to-noise ratio of back-EMF, 2) the operation range of a BLDC motor, and 3) the torque characteristics. The proposed sensorless motor driver is verified through simulations and experiments.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1034-1035
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• 2015

Watertight 25.8 kV/600 A/12.5 kA fault current limiters (FCLs) have successfully installed in five areas (Incheon, Seoul, Gyeong-gi, Daejeon, Suwon) on KEPCO power distribution line for the purpose of commercial demonstrations. The fault current limiting operation of this FCL, which includes functions of sensing, commutation, and reduction of fault currents, is perfectly completed within 1 cycle immediately after fault occurs. The performance of FCL was verified by short circuit test, impedance test, insulation test, temperature-rise test, and control test, etc at PT&T in LS industrial systems, which is the official certification institute in Korea. In 2013, and also the FCL field test was performed in order to test the protection coordination between conventional relays and FCL, on the 1.5 kA and 5.0 kA faults, which were made by connecting the Artificial Fault Generator (AFG) to the distribution line in test grid at KEPCO Power Testing Center. The next step of this project is to check the FCL conditions caused by real external environment, and acquire the various data from five regions installed with FCL. In this paper, we intend to explain the FCL specifications and performance characteristics, and check the expected effect by application of FCL to power distribution line based on the power system analysis of an application site.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.2
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• pp.63-69
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• 2018

In this paper, the operation principle of a bi-directional switch type resonant AC link snubber circuit was described, together with the practical design procedure, which employs in the proposed power module bridge package type resonant AC link snubber. The novel prototype of power module bridge package type resonant AC link snubber-assisted voltage type sinewave soft switching PWM inverter using IGBT power module was demonstrated herein. It was verified that both the auxiliary power switches in this resonant AC link snubber circuit and the main power switches commutate under the condition of soft switching commutation principle. In addition, the power losses of the new soft switching inverter treated here were analyzed by implementing the experimental data of the IGBT and diode v-i characteristics in addition to switching power loss characteristics into our original computer simulation software developed by the authors. Then, the voltage type sinewave soft switching PWM inverter was high efficiency than that of hard switching PWM inverter, along with performance operation waveforms. In the future, the comparative feasibility study of power module bridge type resonant AC link snubber and its related soft switching inverter in addition to the other types resonant snubber assisted soft switching inverter should be done from a practical point of view.

• Journal of Advanced Marine Engineering and Technology
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• v.17 no.5
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• pp.71-85
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• 1993

The Cycloconverter that the author is going to treat in this paper, has strong advantages over the D.C. Link Inverter in points of chattering torque problem and natural commutation. Thus, the Cycloconverter is expected to be well applied to large and low-speed machines which require better speed control at low frequency. But the control circuit of Cycloconverter has two weak points described as follows. 1) Because of its rather complicated control circuit, it is likely to be illoperating due to unexpected noise signals, thus the higher the accuracy and reliability of the circuit is required to be, the more the circuit may cost. 2) Because the load current is not purely sinusoidal, the Cycloconverter may possibly be destroyed in case of inaccurate convert switching resulted from the difficulties in detecting the load current-zero and the current direction at the moment. In this paper, the author first of all intends to design and build a modified VVVF-type Noncirculating Current Cycloconverter to which recently proposed control methods are applied for improving the circuit simplicity, the control performance, and the system reliability. And then, experiments for observing the output waveforms of the Cycloconverter which is controlled by Singled-Board Computer using 8086 16-bit microprocesser are carried out. Finally the author concludes the result of this study as follows. 1) By replacing the conventional analog control circuits such as Reference Wave Generator, Cosine Timing Wave Generator, and Comparator with softwares, a great circuit simplicity is achieved. 2) The output of the designed Cycloconverter changes its frequency very fast without showing discontinuity of its waveform, and this waveform characteristics enables the smooth speed control of Induction Motor. 3) The design control circuit of Cycloconverter can be applied to the systems of 12 or 24 pulses because of its short processing period.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.5B no.4
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• pp.366-373
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• 2005

This paper presents two new circuit topologies of the dc busline side active resonant snubber assisted voltage source high frequency link soft switching PWM full-bridge dc-dc power converters acceptable for either utility ac 200V-rms or ac 400V-rms input grid. These high frequency switching dc-dc converters proposed in this paper are composed of a typical voltage source-fed full-bridge PWM inverter, high frequency transformer with center tap, high frequency diode rectifier with inductor input filter and dc busline side series switches with the aid of a dc busline parallel capacitive lossless snubber. All the active switches in the full-bridge arms as well as dc busline snubber can achieve ZCS turn-on and ZVS turn-off transition commutation with the aid of a transformer leakage inductive component and consequently the total switching power losses can be effectively reduced. So that, a high switching frequency operation of IGBTs in the voltage source full bridge inverter can be actually designed more than about 20 kHz. It is confirmed that the more the switching frequency of full-bridge soft switching inverter increases, the more soft switching PWM dc-dc converter with a high frequency transformer link has remarkable advantages for its power conversion efficiency and power density implementations as compared with the conventional hard switching PWM inverter type dc-dc power converter. The effectiveness of these new dc-dc power converter topologies can be proved to be more suitable for low voltage and large current dc-dc power supply as arc welding equipment from a practical point of view.

• Progress in Superconductivity
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• v.10 no.1
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• pp.60-67
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• 2008

We present domestic efforts for superconducting fault current limiter (SFCL) application in the Korea Electric Power Corporation (KEPCO) grid and pending points at issue. KEPCO's decision to upgrade the 154 kV/22.9 kV main transformer from 60 MVA to 100 MVA cast a problem of high fault current in the 22.9 kV distribution lines. The grid planners supported adopting an SFCL to control the fault current. This environment friendly to SFCL application must be highly dependent upon the successful development of SFCL having specifications that domestic utility required. The required conditions are (1) small size of not greater than twice of 22.9 kV gas insulated switch-gear (GIS), (2) sustainability of current limitation without the line breaking by circuit breakers (CB) for maximum 1.5 seconds. Also, optionally, recommended is (3) the reclosing capability. Conventional resistive SFCLs do not meet (1) $\sim$ (3) all together. A hybrid SFCL is an excellent solution to meet the conditions. The hybrid SFCL consists of HTS SFCL components for fault detection and line commutation, a fast switch (FS) to break the primary path, and a limiter. This characteristic structure not only enables excellent current limiting performances and the reclosing capability, but also allows drastic reduction of HTS volume and small size of the cryostat, resulting in economic feasibility and compactness of the equipment. External current limiter also enables long term limitation since it is far less sensitive to heat generation than HTS. Semi-active operation is another advantage of the hybrid structure. We will discuss more pending points at issues such as maintenance-free long term operation, small size to accommodate the in-house substation, passive and active control, back-up plans, diagnosis, and so on.

• International Journal of Automotive Technology
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• v.4 no.2
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• pp.65-75
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• 2003

A HEV evaluation program, funded by ADEME, was carried out by a group of Laboratories of different specialties in order to evaluate and compare consumption, emission and component technologies of the three first HEVs put on the market (Toyota Prius, Nissan Tino and Honda Insight). This paper presents the results obtained until now. These results show good consumption and emission performance of the tested vehicles compared to conventional ones. The energy management seems to be globally the same for the three vehicles excepting for cold stans where the Insight allows a very earlier stop of the engine compared to the Tino and especially to the Prius. A mapping of the engine consumption of the Prius and the Insight was performed in order to furnish data for the simulation models. The Permanent Magnet motors of the Prius and Tino have different number of pair poles and then different emf at a given speed. The low emf values of the Prius allow operation at high speed with less field weakening control than for the Tino. The inverters of the Prius and the Tino, controlled by a PWM at respectively 5 kHz and 7 kHz switching frequency, are made of IGBTs with high commutation performances.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.