• 제목/요약/키워드: communication architecture

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Improved Selective Randomized Load Balancing in Mesh Networks

  • Zhang, Xiaoning;Li, Lemin;Wang, Sheng;Yang, Fei
    • ETRI Journal
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    • 제29권2호
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    • pp.255-257
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    • 2007
  • We propose an improved selective randomized load balancing (ISRLB) robust scheme under the hose uncertainty model for a special double-hop routing network architecture. The ISRLB architecture maintains the resilience properties of Valiant's load balancing and reduces the network cost/propagation delay in all other robust routing schemes.

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원전 안전통신망을 위한 결정론적 데이터 통신 구조 (Deterministic Data Communication Architecture for Safety-Critical Networks in Nuclear Power Plants)

  • 박성우;김동훈
    • 대한전기학회논문지:시스템및제어부문D
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    • 제55권5호
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    • pp.199-204
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    • 2006
  • To develop a safety-critical network in nuclear power plants that puts more stringent requirements than the competitive commercial ones do, we establish four design criteria - deterministic communication, explicit separation/isolation structure, reliability, verification & validation. According to those design criteria, the fundamental design elements are chosen as follows - a star topology, point-to-point physical link, connection-oriented link control and fixed allocation access control. After analyzing the design elements, we also build a communication architecture with TDM (Time Division Multiplexing) bus switching scheme. Finally, We develop a DDCNet (Deterministic Data Communication Network) based on the established architecture. The DDCNet is composed of 64 nodes and guarantees the transmission bandwidth of 10Mbps and the delay of 10 msec for each node. It turns out that the DDCNet satisfies the aforementioned design criteria and can be adequately utilized for our purpose.

Frame Memory 축소를 위한 DWT와 Color Conversion 기반의 Overdrive 구조 (Overdrive Architecture using DWT and Color Conversion for Frame Memory Reduction)

  • 변진수;김현섭;김도석;김보관
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2008년도 하계종합학술대회
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    • pp.997-998
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    • 2008
  • In this paper, we proposed a reduced memory overdrive architecture. Proposed overdrive architecture consists of 2D-DWT filter, BLI and Color Conversion block. For Frame Memory reduction we eliminated HH data in DWT-IDWT process and converted color space RGB into YCbCr. Consequently, we reduced Frame Memory about 50%.

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MIMO Architecture for Optical Camera Communications

  • Le, Nam-Tuan;Jang, Yeong Min
    • 한국통신학회논문지
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    • 제42권1호
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    • pp.8-13
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    • 2017
  • Compare with other communication system based RF technology, Optical Camera Communication (OCC) has limitation on data rate due to the low frame rate of camera. The limitation on data rate can be solved with multiple-input and multiple-output (MIMO) technology; and it is the final target of all researches on OCC. The MIMO topology can be implemented easily without breaking out the architecture of image sensor. For image sensor classification, there are two architectures have been developed: rolling shutter and global shutter. The operation of two techniques is different so the performance is also different. In this paper we analyze and evaluate the performance of the MIMO architecture for OCC.

Three Dimensional Networked Virtual Reailty Architecture Enabling Flexible Configuration Based on Function Distribution

  • Yasuyuki-KIYOSUE;Shohei-SUGAWARA;Shigeki-MASAKI;Susumu-ICHINOSE
    • 한국방송∙미디어공학회:학술대회논문집
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    • 한국방송공학회 1999년도 KOBA 방송기술 워크샵 KOBA Broadcasting Technology Workshop
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    • pp.23.1-28
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    • 1999
  • InterSpaceTM is an advanced networked virtual reality system that presents shared three-dimensional computer graphics (CG) worlds via the Internet where multiple users can enjoy synchronous communications with voice, video and text. Users can control their avatars as a surrogate interface. In InterSpace users can walk around and interact with other people and interact with contents. In this paper, we describe the function-distributed architecture used in InterSpace. The architecture enables flexible configuration of server functions and load distribution. It also allows users to select media and client PCs to switch servers dynamically.

효율적인 다중 채널 On-Chip-Bus를 위한 SoC Network Architecture (SoC Network Architecture for Efficient Multi-Channel On-Chip-Bus)

  • 이상헌;이찬호;이혁재
    • 대한전자공학회논문지SD
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    • 제42권2호
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    • pp.65-72
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    • 2005
  • 공정기술과 EDA 툴의 발전에 따라서 하나의 실리콘 다이(Die)에 많은 IP가 집적되고 멀티프로세서가 포함되는 SoC 구조가 가능해지고 있다 그러나 대부분의 기존 SoC 버스는 공유버스 구조라는 문제점으로 인해 통신의 병목현상이 발생하고 이는 전체 시스템 성능을 저하시키는 요인이 된다. 많은 경우에 멀티프로세서 시스템의 성능은 CPU 자체의 속도보다는 효율적인 통신과 균형있는 연산의 분배가 좌우하게 된다 따라서 충분한 SoC 버스 대역폭(Bandwidth)을 확보하기 위한 하나의 해결책으로 크로스바 라우터(Crossbar Router)를 이용하여 효율적인 온 칩 버스구조인 SoC Network Architecture(SNA)를 제안한다. 제안된 SNA구조는 다중 마스터(multi-master)에 대해 다중 채널(multi-channel)을 제공하여 통신의 병목현상을 크게 줄일 수 있으며 뛰어난 확장성을 지원한다. 제안된 구조에 따라 모델 시스템을 설계하고 시뮬레이션을 진행한 결과 AMBA AHB 버스에 비해 평균 $40\%$ 이상 효율이 증가했다.

현대 상업공간 실내디자인에 나타나는 오나먼트의 표상성에 관한 연구 (A Study on the Ornamental Representation in Contemporary Commercial Space)

  • 한혜신;김문덕
    • 한국실내디자인학회논문집
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    • 제18권6호
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    • pp.133-141
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    • 2009
  • Since Adolf Loos' Ornament and Crime was released, ornament had been regarded as a vice in Modern architecture. In Post Modern architecture, the ornamental vocabularies extracted from the classical architecture have been symbolically expressed. As a result, the significance of existence of and the use value of architecture have increased with improved intimacy to the public. However, many studies that have analyzed architecture in terms of semantics and semiotics focusing on communication between architecture and the public have admitted instability in architectural meaning because of the fundamental difference between architecture and language. At the same time, the architectural representation has encountered a lot of limitations along with the deconstruction and non-presentation theory in Post-Structuralism. Even under these circumstances, the ornamental representation can be a critical factor which makes communication possible while expressing spatial identity in this pluralistic contemporary society. Hence, this paper has established logical grounds for research based on theoretical investigation on the concept of representation, semiotics, and ornamental representation, with regard to spatial communication through ornamental representation in commercial space. Based on Peirce's Semiotics which is the typical theoretical science in terms of representation, this paper has analyzed the three kinds of signs (Icon, Index and Symbol) that he proposed. Peirce's classification of signs becomes ideal when the factors are well balanced, with room for combination instead of strict classification. It appears that his theory of signs would be useful in understanding and analyzing ornamental representation. This study on representational ornament could offer a plan for ideal communication and abundant spatial experience in the interior design of commercial space in which the expression of creative space identity is required.

Smart Grid Cooperative Communication with Smart Relay

  • Ahmed, Mohammad Helal Uddin;Alam, Md. Golam Rabiul;Kamal, Rossi;Hong, Choong Seon;Lee, Sungwon
    • Journal of Communications and Networks
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    • 제14권6호
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    • pp.640-652
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    • 2012
  • Many studies have investigated the smart grid architecture and communication models in the past few years. However, the communication model and architecture for a smart grid still remain unclear. Today's electric power distribution is very complex and maladapted because of the lack of efficient and cost-effective energy generation, distribution, and consumption management systems. A wireless smart grid communication system can play an important role in achieving these goals. In this paper, we describe a smart grid communication architecture in which we merge customers and distributors into a single domain. In the proposed architecture, all the home area networks, neighborhood area networks, and local electrical equipment form a local wireless mesh network (LWMN). Each device or meter can act as a source, router, or relay. The data generated in any node (device/meter) reaches the data collector via other nodes. The data collector transmits this data via the access point of a wide area network (WAN). Finally, data is transferred to the service provider or to the control center of the smart grid. We propose a wireless cooperative communication model for the LWMN.We deploy a limited number of smart relays to improve the performance of the network. A novel relay selection mechanism is also proposed to reduce the relay selection overhead. Simulation results show that our cooperative smart grid (coopSG) communication model improves the end-to-end packet delivery latency, throughput, and energy efficiency over both the Wang et al. and Niyato et al. models.

Non-SQL 질의 데이터 서버 아키텍처 (An Architecture for Data Server of Non SQL Query)

  • K. H., Kwon;Chakra, Balayar;S. H., Cheon
    • 한국정보과학회:학술대회논문집
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    • 한국정보과학회 2004년도 가을 학술발표논문집 Vol.31 No.2 (2)
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    • pp.406-408
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    • 2004
  • To develop enterprise architecture based distributed application needs consideration of various factors such as division of role between web-designer and software developer, defining entity and its usage, database connection and transaction processing. This paper presents DONSL(Data Server of Non SQL-Query) architecture that provides solution to above aspects through web-tier object modeling guaranteeing efficient transaction processing and performance between web-tier and 08MS through simplified usage of query logic property.

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무선 통신용 Dual-Modulus Prescaler 위상고정루프(PLL)의 간단한 분주 구조 (Simple Dividing Architecture of Dual-Modulus Prescaler Phase-Locked Loop for Wireless Communication)

  • 김태우;이순섭;최광석;김수원
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 추계종합학술대회 논문집
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    • pp.271-274
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    • 1999
  • This paper proposes a simple architecture of digital dividing block in dual-modulus prescaler phase-locked loop used in the wireless communication. Proposed architecture eliminates a swallow counter in the conventional one and demonstrates the advantages in reducing the power consumption and the gate-counts. Therefore, it is suitable for small die area and low power applications. The circuit is designed in a standard 0.35${\mu}{\textrm}{m}$ CMOS process.

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