• Title/Summary/Keyword: code complexity

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An analysis of optimal design conditions of LDPC decoder for IEEE 802.11n Wireless LAN Standard (IEEE 802.11n 무선랜 표준용 LDPC 복호기의 최적 설계조건 분석)

  • Jung, Sang-Hyeok;Na, Young-Heon;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.4
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    • pp.939-947
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    • 2010
  • The LDPC(Low-Density Parity-Check) code, which is one of the channel encoding methods in IEEE 802.11n wireless LAN standard, has superior error-correcting capabilities. Since the hardware complexity of LDPC decoder is high, it is very important to take into account the trade-offs between hardware complexity and decoding performance. In this paper, the effects of LLR(Log-Likelihood Ratio) approximation on the performance of MSA(Min-Sum Algorithm)-based LDPC decoder are analyzed, and some optimal design conditions are derived. The parity check matrix with block length of 1,944 bits and code rate of 1/2 in IEEE 802.11n WLAN standard is used. In the case of $BER=10^{-3}$, the $E_b/N_o$ difference between LLR bit-widths (6,4) and (7,5) is 0.62 dB, and $E_b/N_o$ difference for iteration cycles 6 and 7 is 0.3 dB. The simulation results show that optimal BER performance can be achieved by LLR bit-width of (7,5) and iteration cycle of 7.

A new efficient algorithm for test pattern compression considering low power test in SoC (SoC환경에서의 저전력 테스트를 고려한 테스트 패턴 압축에 대한 효율적인 알고리즘)

  • 신용승;강성호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.9
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    • pp.85-95
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    • 2004
  • As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

A Study on the Selection of Test Scope and the Prioritization of Test Case Based on Modification Method for Regression Testing (변경 메서드 기반의 회귀 테스트 검증 범위 선택 및 검증 항목 우선순위 선정에 관한 연구)

  • Jung, Woo-Jin;Rah, Sang-Rin;Choi, Yong-Lak
    • Journal of Information Technology Services
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    • v.14 no.2
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    • pp.129-142
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    • 2015
  • The purpose of this study is to suggest an effective regression testing method in order to minimize the scope of test resulting from the modification of software and to prevent mismatch of test case and test objects. As a way to improve the efficiency of regression testing which uses a change-centric testing technique, the method flow is analyzed and grasped through a static analysis based on source code in order to identify modified parts. After the order of priority is set according to the results of user action log-based dynamic analysis on identified regression testing objects, test effect can be raised by adjusting the order of priority using code complexity. Quality assurance coverage can be checked using the user action log suggested in this study, and the progress of test and whether or not each function has been verified can be checked, too. In addition, by minimizing test parts and adjusting the order of test, costs and time can be saved, making it possible to conduct regression testing effectively.

Complexity Analysis of a VHDL Implementation of the Bit-Serial Reed-Solomon Encoder (VHDL로 구현된 직렬승산 리드솔로몬 부호화기의 복잡도 분석)

  • Back Seung hun;Song Iick ho;Bae Jin soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.3C
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    • pp.64-68
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    • 2005
  • Reed-Solomon code is one of the most versatile channel codes. The encoder can be implemented with two famous structures: ordinary and bit-serial. The ordinary encoder is generally known to be complex and fast, while the bit-serial encoder is simple and not so fast. However, it may not be true for a longer codeword length at least in VHDL implementation. In this letter, it is shown that, when the encoder is implemented with VHDL, the number of logic gates of the bit-serial encoder might be larger than that of the ordinary encoder if the dual basis conversion table has to be used. It is also shown that the encoding speeds of the two VHDL implemented encoders are exactly same.

Development of a Rapid Control Prototyping Platform for Engine Control System (엔진 제어시스템을 위한 래피드 콘트롤 프로토타이핑 플랫폼에 관한 연구)

  • 송정현;이우택;선우명호
    • Transactions of the Korean Society of Automotive Engineers
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    • v.11 no.1
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    • pp.160-165
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    • 2003
  • The design and implementation of an engine control system has become an important area in developing a new car, but the implementation of an engine control system is becoming a tedious and time-consuming work as the level of complexity increases. In order to shorten the development cycle of the control system, rapid control prototyping (RCP) technique deserves developers' attention. A new RCP platform has been developed for an automotive engine control application. This prototyping system strictly adheres to the layered architecture of the final production ECU, and separates the automatically generated part of software, or the application area, from the hand coded area, which generally carefully designed and tested because of the hardware dependency and the efficiency of microcontroller. The $Matlab{\circledR}$ tool-chain of Mathworks Inc. has been selected as a base environment in this study. A newly developed Engine Control Toolbox of Real-Time $Workshop{\circledR}$ converts a graphically represented control algorithm into optimized application codes and links them with other parts of the software to generate executable code for the target processor.

Erasure decoding strategies for RS product code reducing undetected error rate (검출 불능 오류율을 향상기키는 Reed-Solomon 적부호의 이레이져 복호방법)

  • 김정헌;염창열;송홍엽;강구호;김순태;백세현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.4B
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    • pp.427-436
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    • 2001
  • RS product codes are widely used in digital storage systems. There are lots of decoding strategies for product code for short-length RS codes. Unfortunately many of them cannot be applied to long-length RS product codes because of the complexity of decoder. This paper proposes new decoding strategies which can be used in long length RS product codes.

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Performance and Convergence Analysis of Tree-LDPC codes on the Min-Sum Iterative Decoding Algorithm (Min-Sum 반복 복호 알고리즘을 사용한 Tree-LDPC의 성능과 수렴 분석)

  • Noh Kwang-seok;Heo Jun;Chung Kyuhyuk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.1C
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    • pp.20-25
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    • 2006
  • In this paper, the performance of Tree-LDPC code is presented based on the min-sum algorithm with scaling and the asymptotic performance in the water fall region is shown by density evolution. We presents that the Tree-LDPC code show a significant performance gain by scaling with the optimal scaling factor which is obtained by density evolution methods. We also show that the performance of min-sum with scaling is as good as the performance of sum-product while the decoding complexity of min-sum algorithm is much lower than that of sum-product algorithm. The Tree-LDPC decoder is implemented on a FPGA chip with a small interleaver size.

Building a Code Visualization Process to Extract Bad Smell Codes (배드 스멜 코드 추출을 위한 코드 가시화 프로세스 구축)

  • Park, Jihoon;Park, Bo Kyung;Kim, Ki Du;Kim, R. Young Chul
    • KIPS Transactions on Software and Data Engineering
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    • v.8 no.12
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    • pp.465-472
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    • 2019
  • Today, in many area the rise of software necessity there has been increasing the issue of the impotance of Good Software. Our reality in software industrial world has been happening to frequently change requirements at any stage of software life cycle. Furthermore this frequent changing will be increasing the design complexity, which will result in being the lower quality of software against our purpose the original design goals. To solve this problem, we suggest how to improve software design through refactoring based on reverse engineering. This is our way of diverse approaches to visually identify bad smell patterns in source code. We expect to improve software quality through refactoring on even frequently changing requirements.

Development of an Unsteady Aerodynamic Analysis Module for Rotor Comprehensive Analysis Code

  • Lee, Joon-Bae;Yee, Kwan-Jung;Oh, Se-Jong;Kim, Do-Hyung
    • International Journal of Aeronautical and Space Sciences
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    • v.10 no.2
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    • pp.23-33
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    • 2009
  • The inherent aeromechanical complexity of a rotor system necessitated the comprehensive analysis code for helicopter rotor system. In the present study, an aerodynamic analysis module has been developed as a part of rotorcraft comprehensive program. Aerodynamic analysis module is largely classified into airload calculation routine and inflow analysis routine. For airload calculation, quasi-steady analysis model is employed based on the blade element method with the correction of unsteady aerodynamic effects. In order to take unsteady effects - body motion effects and dynamic stall - into account, aerodynamic coefficients are corrected by considering Leishman-Beddoes's unsteady model. Various inflow models and vortex wake models are implemented in the aerodynamic module to consider wake induced inflow. Specifically, linear inflow, dynamic inflow, prescribed wake and free wake model are integrated into the present module. The aerodynamic characteristics of each method are compared and validated against available experimental data such as Elliot's induced inflow distribution and sectional normal force coefficients of AH-1G. In order to validate unsteady aerodynamic model, 2-D unsteady model for NACA0012 airfoil is validated against aerodynamic coefficients of McAlister's experimental data.

Random Assignment-Transmitter-Based Protocol for Centralized Stread-Spectrum Packet Radio Networks (중앙집중 대역확산 패킷라디오 네트워크를 위한 임의할당-송신기 프로토콜)

  • 노준철;김동인
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.4
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    • pp.729-739
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    • 1994
  • In a centralized spread-spectrum packet radio network, a random assignment -transmitter-based spreading code protocol(RA-T) is proposed which permits the contention mode only in the trasmission of a preamble while avoiding collision during the data packet transmission by assigning near-orthogonal spreading codes to each user. Compared to the conventional transmitter-based code scheme, this scheme allows reduction in receiver complexity when only a small number of distinct spreading codes are employed for the preamble transmission. Throughout theoretical and simulation results, it is shown that the use of the RA-T scheme with just two or three distinct codes for the preamble packet achieves most of the performance gain.

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