• Title/Summary/Keyword: code complexity

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Efficient Hybrid ARQ with Space-Time Coding and Low-Complexity Decoding (Space-Time Coding과 낮은 복잡도의 복호 방범을 사용한 효과적인 Hybrid ARQ 기법)

  • Oh Mi-Kyung;Kwon Yeong-Hyen;Park Dong-Jo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.12C
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    • pp.1222-1230
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    • 2005
  • We aim at increasing the throughput of the hybrid automatic retransmission request (HARQ) protocol in Space-Time (ST) coded multi-antenna transmission systems. By utilizing reliability information at the decoder, we obtain an improved probability of successful decoding, which enhances the overall system throughput at low-complexity. Simulations and analytical results demonstrate the performance of our scheme in impulse noise environment as well as AWGN and fading multi-input multi-ouput (MIMO) channels.

Simple Blind Channel Estimation Scheme for Downlink MC-CDMA Systems (하향링크 MC-CMDMA 시스템을 위한 간단한 미상 채널 추정 방법)

  • Seo, Bang-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37 no.6A
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    • pp.480-487
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    • 2012
  • In multicarrier code-division multiple access (MC-CDMA) systems, conventional blind channel estimation schemes require the inverse matrix calculation or eigenvalue decomposition of the received signal covariance matrix. Therefore, computational complexity of the conventional schemes is too high and they cannot be employed in downlink systems. In this paper, we propose a simple blind channel estimation scheme with very low computational complexity. Simulation results show that the proposed scheme has better channel estimation and bit error rate (BER) performance than the conventional schemes.

A Study on Inter Prediction Mode Determination using the Variance in the Motion Vectors (움직임 벡터의 변화량을 이용한 인터 예측 모드 결정에 관한 연구)

  • Kim, June;Kim, Youngseop
    • Journal of the Semiconductor & Display Technology
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    • v.13 no.1
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    • pp.109-112
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    • 2014
  • H.264/AVC is an international video coding standard that is established in cooperation with ITU-T VCEG and ISO/IEC MPEG, which shows improved code and efficiency than the previous video standards. Motion estimation using various macroblock from 44 to 1616 among the compression techniques of H.264/AVC contributes much to high compression efficiency. Generally, in the case of small motion vector or low complexity about P slice is decided $P16{\times}16$ mode encoding method. But according to circumstances, macroblock is decided $P16{\times}16$ mode despite large motion vector. If the motion vector variance is more than threshold and final select mode is $P16{\times}16$ mode, it is switched to $P8{\times}8$ mode, so this paper shows that the storage capacity is reduced. The results of experiment show that the proposed algorithm increases the compression efficiency of the H.264/AVC algorithm to 0.4%, even reducing the time and without increasing complexity.

Design and Performance Analysis of a DS/CDMA Multiuser Detection Algorithm in a Mixed Structure Form (혼합구조 형태의 DS/CDMA 다중사용자 검파 알고리즘 설계 및 성능 분석)

  • Lim, Jong-Min
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.39 no.3
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    • pp.51-58
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    • 2002
  • The conventional code division multiple access(CDMA) detector shows severe degradation in communication quality as the number of users increases due to multiple access interferences(MAI). This problem thus restricts the user capacity. Various multiuser detection algorithms have been proposed to overcome the MAI problem. The existing detectors can be generally classified into one of the two categories : linear multiuser detection and subtractive interference cancellation detectors. In the linear multiuser detection, a linear transform is applied to the soft outputs of the conventional detector. In the subtractive interference cancellation detection, estimates of the interference are generated and subtracted out from the received signal. There has been great interest in the family of the subtractive interference cancellation detection because the linear multiuser detection exhibits the disadvantage of taking matrix inversion operations. The successive interference cancellation (SIC) and the parallel interference cancellation (PIC) are the two most popular structures in the subtractive interference cancellation detector. The SIC structure is very simple in hardware complexity, but has the disadvantage of increased processing delay time, while the PIC structure is good in performance, but shows the disadvantage of increased hardware complexity. In this paper we propose a mixed structure form of SIC and PIC in order to achieve good performance as well as simple hardware complexity. A performance analysis of the proposed scheme has been made, and the superior characteristics of the mixed structure are demonstrated by extensive computer simulations. 

Performance Analysis of Multicarrier Code Selection CDMA System for PAPR Reduction in Multipath Fading Channel (PAPR을 줄이기 위한 Multicarrier Code Select CDMA시스템의 다중 경로 페이딩 채널에서 성능 분석)

  • Ryu Kwan Woong;Park Yong Wan;Hong Een Kee;Kim Myovng Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.12A
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    • pp.1319-1332
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    • 2004
  • Multicarrier direct sequence code-division multiple access CDMA(MC DS-CDMA) is an attractive technique for achieving high data rate transmission even if the potentially large peak-to-average power ratio(PAPR) is an important factor for its application. On the other hand, code select CDMA(CS-CDMA) is an attractive technique with constant amplitude transmission of multicode signal irregardless of subchannels by introducing code selection method. In this paper we propose a new multiple access scheme based on the combination of MC DS-CDMA and CS-CDMA. Proposed scheme, which we called MC CS-CDMA, includes the sutclasses of MC DS-CDMA and CS-CDMA as special cases. The performance of this system is investigated for multipath Sequency selective fading channel and maximal ratio combining with rake receiver. In addition the PAPR of proposed system is compare with that of both MC BS-CDMA and CS-CDMA. Simulation results show that proposed system improves PAPR reduction than MC DS-CDMA at the expense of the complexity of receiver and the number of available non. Also, the numerical result shows that the proposed system is better performance than MC DS-CDMA due to the increasing processing gain and the number of time diversity gain.

Upper Bounds for the Performance of Turbo-Like Codes and Low Density Parity Check Codes

  • Chung, Kyu-Hyuk;Heo, Jun
    • Journal of Communications and Networks
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    • v.10 no.1
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    • pp.5-9
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    • 2008
  • Researchers have investigated many upper bound techniques applicable to error probabilities on the maximum likelihood (ML) decoding performance of turbo-like codes and low density parity check (LDPC) codes in recent years for a long codeword block size. This is because it is trivial for a short codeword block size. Previous research efforts, such as the simple bound technique [20] recently proposed, developed upper bounds for LDPC codes and turbo-like codes using ensemble codes or the uniformly interleaved assumption. This assumption bounds the performance averaged over all ensemble codes or all interleavers. Another previous research effort [21] obtained the upper bound of turbo-like code with a particular interleaver using a truncated union bound which requires information of the minimum Hamming distance and the number of codewords with the minimum Hamming distance. However, it gives the reliable bound only in the region of the error floor where the minimum Hamming distance is dominant, i.e., in the region of high signal-to-noise ratios. Therefore, currently an upper bound on ML decoding performance for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix cannot be calculated because of heavy complexity so that only average bounds for ensemble codes can be obtained using a uniform interleaver assumption. In this paper, we propose a new bound technique on ML decoding performance for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix using ML estimated weight distributions and we also show that the practical iterative decoding performance is approximately suboptimal in ML sense because the simulation performance of iterative decoding is worse than the proposed upper bound and no wonder, even worse than ML decoding performance. In order to show this point, we compare the simulation results with the proposed upper bound and previous bounds. The proposed bound technique is based on the simple bound with an approximate weight distribution including several exact smallest distance terms, not with the ensemble distribution or the uniform interleaver assumption. This technique also shows a tighter upper bound than any other previous bound techniques for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix.

New Low-Power and Small-Area Reed-Solomon Decoder (새로운 저전력 및 저면적 리드-솔로몬 복호기)

  • Baek, Jae-Hyun;SunWoo, Myung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.96-103
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    • 2008
  • This paper proposes a new low-power and small-area Reed-Solomon decoder. The proposed Reed-Solomon decoder using a novel simplified form of the modified Euclid's algorithm can support low-hardware complexity and low-Power consumption for Reed-Solomon decoding. The simplified modified Euclid's algorithm uses new initial conditions and polynomial computations to reduce hardware complexity, and thus, the implemented architecture consisting of 3r basic cells has the lowest hardware complexity compared with existing modified Euclid's and Berlekamp-Massey architectures. The Reed-Solomon decoder has been synthesized using the $0.18{\mu}m$ Samsung standard cell library and operates at 370MHz and its data rate supports up to 2.9Gbps. For the (255, 239, 8) RS code, the gate counts of the simplified modified Euclid's architecture and the whole decoder excluding FIFO memory are only 20,166 and 40,136, respectively. Therefore, the proposed decoder can reduce the total gate count at least 5% compared with the conventional DCME decoder.

Design of Low Complexity and High Throughput Encoder for Structured LDPC Codes (구조적 LDPC 부호의 저복잡도 및 고속 부호화기 설계)

  • Jung, Yong-Min;Jung, Yun-Ho;Kim, Jae-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.10
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    • pp.61-69
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    • 2009
  • This paper presents the design results of a low complexity and high throughput LDPC encoder structure. In order to solve the high complexity problem of the LDPC encoder, a simplified matrix-vector multiplier is proposed instead of the conventional complex matrix-vector multiplier. The proposed encoder also adopts a partially parallel structure and performs column-wise operations in matrix-vector multiplication to achieve high throughput. Implementation results show that the proposed architecture reduces the number of logic gates and memory elements by 37.4% and 56.7%, compared with existing five-stage pipelined architecture. The proposed encoder also supports 800Mbps throughput at 40MHz clock frequency which is improved about three times more than the existing architecture.

Efficient Correlation Channel Modeling for Transform Domain Wyner-Ziv Video Coding (Transform Domain Wyner-Ziv 비디오 부호를 위한 효과적인 상관 채널 모델링)

  • Oh, Ji-Eun;Jung, Chun-Sung;Kim, Dong-Yoon;Park, Hyun-Wook;Ha, Jeong-Seok
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.47 no.3
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    • pp.23-31
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    • 2010
  • The increasing demands on low-power, and low-complexity video encoder have been motivating extensive research activities on distributed video coding (DVC) in which the encoder compresses frames without utilizing inter-frame statistical correlation. In DVC encoder, contrary to the conventional video encoder, an error control code compresses the video frames by representing the frames in the form of syndrome bits. In the meantime, the DVC decoder generates side information which is modeled as a noisy version of the original video frames, and a decoder of the error-control code corrects the errors in the side information with the syndrome bits. The noisy observation, i.e., the side information can be understood as the output of a virtual channel corresponding to the orignal video frames, and the conditional probability of the virtual channel model is assumed to follow a Laplacian distribution. Thus, performance improvement of DVC systems depends on performances of the error-control code and the optimal reconstruction step in the DVC decoder. In turn, the performances of two constituent blocks are directly related to a better estimation of the parameter of the correlation channel. In this paper, we propose an algorithm to estimate the parameter of the correlation channel and also a low-complexity version of the proposed algorithm. In particular, the proposed algorithm minimizes squared-error of the Laplacian probability distribution and the empirical observations. Finally, we show that the conventional algorithm can be improved by adopting a confidential window. The proposed algorithm results in PSNR gain up to 1.8 dB and 1.1 dB on Mother and Foreman video sequences, respectively.

Introductions of Pre-Rake with Frequency Domain Equalizer and Cyclic Prefix Reduction Method in CDMA/TDD Multi-code Transmission (CDMA/TDD 다중코드 전송에서 주파수 도메인 등화기와 결합된 Pre-Rake 와 Cyclic Prefix 최소화 방법)

  • Lee, Jun-Hwan;Jeong, In-Cheol
    • Journal of Satellite, Information and Communications
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    • v.6 no.1
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    • pp.86-96
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    • 2011
  • In this paper we propose a Pre-rake system applied with a frequency domain equalizer in TDD/CDMA multi-code transmission. The Pre-rake system has been well known technique in TDD/CDMA to make a receiver simple. However, it still has residual losses of path diversity and signal to noise ratio (SNR). However, gathering all the residual paths demands an additional hardware such as a rake combiner at the receiver. For the reason Pre/Post-rake system has already been proposed at up/downlink correlated channel conditionunder the assumption of noisier channel. There is a trade-off between the first purpose of Pre-rake that makes hardware simple at the receiver and the performance improvement. From the point the frequency domain equalizer (FDE) can be considered in Pre/Post-rake to supply the receiver with the flexible equalizing methods with rather reduced complexity compared with time domain rake combiner or equalizers. Pre-rake itself increases the number of multipath, which results from the convolution of Pre-rake filter and wireless channel, and FDE must be well matched to Pre/Post-rake, while it considers the relationship of hardware complexity and the performance. In this paper, the Pre-rake/Post-FDE system is introduced at TDD/CDMA multi-code transmission. In addition, the cyclic prefix reduction method in the proposed system is introduced, and the theoretical analysis to the proposed system is given by assuming Gaussian approximation, and finally the numerical simulation results are provided.