• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.117-120
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• 2001

This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.204-207
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• 2000

Verification is one of the most critical and time-consuming tasks in today's design process. This paper describes the basic idea of Co-verification and the environment setup for the design of DVD Servo with TeakLite DSP core by using Seamless CVE, Hardware/software Co-verification too1.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제8권3호
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• pp.261-267
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• 2002

SOC(System On a Chip)에 대한 설계에서 설계 생산성을 향상시키기 위해서 가장 시급히 해결해야 할 과제가 하드웨어뿐만 아니라 소프트웨어가지도 함께 동시검증(co-verification)하여야 함으로서 설계검증에 과도하게 투입되는 비용과 시간을 줄이는 것이다. 본 논문에서는 이러한 설계검증 생산성을 효과적으로 높이기 위한 방법으로 HW/SW 동시검증을 수행할 수 있는 대표적인 두 방법들인 동시-시뮬레이션(co-simulation)과 동시-에뮬레이션(co-emulation)을 강하게 결합한 새로운 검증 방법인 집적 동시검증(integrated co-verification) 방법을 제안하였다. 또한, 상용화된 동시검증 툴인 Seamless CVE와 물리적 프로토타이핑 보드를 함께 사용하여 구성한 ARM/AMBA 플랫폼 기반의 집적 동시검증 환경을 직접 구성하고, 이를 이용하여 제안된 검증기법의 유용성을 실험적으로 확인하였다.

• 융합신호처리학회논문지
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• 제10권4호
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• pp.274-279
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• 2009

시스템수준 설계방법론에서 널리 사용하고 있는 설계흐름도는 시스템명세, 시스템수준의 HW/SW 분할, HW/SW 통합설계, 가상 또는 물리적 프로토타입을 이용한 통합검증, 시스템통합으로 구성된다. 본 논문에서는 SystemVerilog와 SystemC를 기반으로 하여 신속한 기능검증이 가능한 native-code 통합검증환경과 클럭수준 검증까지 가능한 계층화 통합검증환경을 각각 구현하였다. Native-code 통합검증환경은 시스템수준 설계언어인 SystemC를 이용하여 HW/SW 분할단계를 수행한 후, SoC 설계의 HW부분과 SW부분을 각각 SystemVerilog와 SystemC로 모델링하여 상호작용을 하나의 시뮬레이션 프로세스로 검증한다. 계층화된 SystemVerilog 테스트벤치는 임의의 테스트벡터를 생성하여 DUT의 모서리 시험을 포함하는 검증환경으로 본 논문에서는 SystemC를 도입하여 다중 상속을 가지는 통합검증환경의 구성요소를 먼저 설계한 후, SystemVerilog DPI와 ModelSim 매크로를 이용하여 SystemVerilog 테스트벤치와 결합된 통합검증환경을 설계한다. 다중 상속은 여러 기초클래스를 결합한 새로운 클래스를 정의하여 코드의 재사용성을 높이는 장점을 가지므로, 본 논문의 SystemC를 도입한 통합검증환경 설계는 검증된 기존의 코드를 재사용할 수 있는 이점을 가진다.

• International Journal of Contents
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• 제7권1호
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• pp.23-28
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• 2011

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

• 한국기후변화학회지
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• 제9권1호
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• pp.69-74
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• 2018

The purpose of this study is to suggest the methodology of $CO_2$ Emission Factor Verification and Quantitative Assessment in Ethylene Product Processes. At first, this study compare the IPCC (Intergovernmental Panel on Climate Change) 1996 Guideline and 2006 Guideline. And analyse methodology for estimating $CO_2$ emission and $CO_2$ emission factor in Ethylene product process. Also analyse cases of estimating $CO_2$ emission factor based on material balance. Methodology of $CO_2$ Emission Factor Verification and Quantitative Assessment are following the categories proposed by GIR (Greenhouse Gas Inventory and Research Center). There are total 12 factors in 8 categories and give 5 or 10 points according to their importance. Also this study suggests necessary data of document to meet the conditions. The result would help estimate accuracy Greenhouse Gas Inventory. Also contribute to establish policy on environmental assessment, air conservation, etc.

• Nuclear Engineering and Technology
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• 제49권5호
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• pp.989-995
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• 2017

Distributed Control System (DCS) communication networks, which use Fast Ethernet with redundant networks for the transmission of information, have been installed in digitalized nuclear power plants. Normally, failover tests are performed to verify the reliability of redundant networks during design and manufacturing phases; however, systematic integrity tests of DCS networks cannot be fully performed during these phases because all relevant equipment is not installed completely during these two phases. In additions, practical verification tests are insufficient, and there is a need to test the actual failover function of DCS redundant networks in the target environment. The purpose of this study is to verify that the failover functions works correctly in certain abnormal conditions during installation and commissioning phase and identify the influence of network failover on the entire DCS. To quantify the effects of network failover in the DCS, the packets (Protocol Data Units) must be collected and resource usage of the system has to be monitored and analyzed. This study introduces the use of a new methodology for verification of DCS network failover during the installation and commissioning phases. This study is expected to provide insight into verification methodology and the failover effects from DCS redundant networks. It also provides test results of network performance from DCS network failover in digitalized domestic nuclear power plants (NPPs).

• 대한전자공학회논문지SD
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• 제39권7호
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• pp.46-56
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• 2002

본 논문에서는 3세대 이동 통신 표준안의 하나인 cdma2000 1x를 지원하는 이동국 모뎀칩 개발에 사용된 하드웨어-소프트웨어 동시 검증 방법과 환경에 대해 기술한다. 하드웨어의 프로토타이핑 없이 레지스터 전송단계의 가상 하드웨어 모델과 물리 계층의 소프트웨어 모델을 채널링크 시뮬레이터, 다기능 테스트벤치와 유기적으로 결합하여 효과적인 통합 검증 환경을 구축함으로써 300만 게이트급의 복잡한 시스템 집적회로 개발 기간과 배용을 대폭 단축하였다.

• 한국지구물리탐사학회:학술대회논문집
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• 한국지구물리탐사학회 2009년도 학술대회 초록집
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• pp.16-19
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• 2009

최근 온실가스감축의 방법으로 이산화탄소 지중저장이 많은 관심을 받고 있다 CO2 지중저장을 위한 부지 선정 및 특성화, CO2 주입에 따른 모니터링 단계 등 지중저장 전 파전에서 지구물리탐사법이 중요한 역활을 담당할 것으로 예상된다. 특히 주입된 CO2의 거동과 누출에 대한 모니터링과 검증기술은 온실가스감축의 인정과 신뢰성 향상에 많은 기여를 할 것으로 기대된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.