• Journal of KIISE:Computing Practices and Letters
• /
• v.8 no.3
• /
• pp.261-267
• /
• 2002

In SOC(System On a Chip) designs, reducing time and cast for design verification is the most critical to improve the design productivity. this is mainly because the designs require co-verifying HW together with SW, which results in the increase of verification complexity drastically. In this paper, to cope with the verification crisis in SOC designs, we propose a new verification methodology, so called integrated co-verification, which lightly combine both co-simulation and co-emulation in unified and seamless way. We have applied our integrated co-verification to ARM/AMBA platform-based co-verification environment with a commercial co-verification tool, Seamless CVE, and a physical prototyping board. The experiments has shown clear advantage of the proposed technique over conventional ones.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.204-207
• /
• 2000

Verification is one of the most critical and time-consuming tasks in today's design process. This paper describes the basic idea of Co-verification and the environment setup for the design of DVD Servo with TeakLite DSP core by using Seamless CVE, Hardware/software Co-verification too1.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.117-120
• /
• 2001

This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.

• Journal of Climate Change Research
• /
• v.9 no.1
• /
• pp.69-74
• /
• 2018

The purpose of this study is to suggest the methodology of $CO_2$ Emission Factor Verification and Quantitative Assessment in Ethylene Product Processes. At first, this study compare the IPCC (Intergovernmental Panel on Climate Change) 1996 Guideline and 2006 Guideline. And analyse methodology for estimating $CO_2$ emission and $CO_2$ emission factor in Ethylene product process. Also analyse cases of estimating $CO_2$ emission factor based on material balance. Methodology of $CO_2$ Emission Factor Verification and Quantitative Assessment are following the categories proposed by GIR (Greenhouse Gas Inventory and Research Center). There are total 12 factors in 8 categories and give 5 or 10 points according to their importance. Also this study suggests necessary data of document to meet the conditions. The result would help estimate accuracy Greenhouse Gas Inventory. Also contribute to establish policy on environmental assessment, air conservation, etc.

• Journal of the Institute of Convergence Signal Processing
• /
• v.10 no.4
• /
• pp.274-279
• /
• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• International Journal of Contents
• /
• v.7 no.1
• /
• pp.23-28
• /
• 2011

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

• Nuclear Engineering and Technology
• /
• v.49 no.5
• /
• pp.989-995
• /
• 2017

Distributed Control System (DCS) communication networks, which use Fast Ethernet with redundant networks for the transmission of information, have been installed in digitalized nuclear power plants. Normally, failover tests are performed to verify the reliability of redundant networks during design and manufacturing phases; however, systematic integrity tests of DCS networks cannot be fully performed during these phases because all relevant equipment is not installed completely during these two phases. In additions, practical verification tests are insufficient, and there is a need to test the actual failover function of DCS redundant networks in the target environment. The purpose of this study is to verify that the failover functions works correctly in certain abnormal conditions during installation and commissioning phase and identify the influence of network failover on the entire DCS. To quantify the effects of network failover in the DCS, the packets (Protocol Data Units) must be collected and resource usage of the system has to be monitored and analyzed. This study introduces the use of a new methodology for verification of DCS network failover during the installation and commissioning phases. This study is expected to provide insight into verification methodology and the failover effects from DCS redundant networks. It also provides test results of network performance from DCS network failover in digitalized domestic nuclear power plants (NPPs).

• Journal of Positioning, Navigation, and Timing
• /
• v.4 no.1
• /
• pp.17-23
• /
• 2015

With the increase in the risk of GPS jamming, the development and application of anti-jamming GPS techniques have been actively performed. As the objective performance verification of developed techniques is important, equipment development for verification and discussion on anti-jamming performance test method and procedure have also been conducted. However, most tests are related to the specification of equipment and therefore detailed procedure of the performance verification of an anti-jamming system needs to be developed. In this study, requirements for anti-jamming performance verification were described, and test configurations and performance evaluation items depending on three kinds of test methods (lab test, basic outdoor test, and chamber test) were suggested for anti-jamming performance verification.

• Journal of KIISE:Software and Applications
• /
• v.37 no.4
• /
• pp.323-339
• /
• 2010

The complexity of embedded systems and the effort to develop them has been rising in proportion with their importance. Also, the heterogeneity of the hardware and software parts in embedded systems makes it more challenging to develop. Errors caused by hardware/software interfaces, especially, account for up to 13 percent of failures with an increasing trend. Therefore, verifying the interface between hardware and software in embedded system is one of the most important research areas. However, current approaches such as co-simulation method and model checking have explicit limitations. In this paper, we propose the synthesizable interface co-verification framework for hardware/software co-design. Firstly, we introduce the separate interface specifications for the heterogeneous components to describe hardware design and software design. Our specifications are expressive enough to describe both. We also provide the transformation rules from the software specification to the hardware specification so that the whole system can be described from the software view. Secondly, we address the solution of verifying the interface of the software and hardware design by adopting and extending existing verification-techniques and extending them. In hardware interface verification, we exploit the model checking technique and provide more efficient verification by closing the hardware design from the assumption of the software behavior which is ensured by software verification step. Lastly, we generate the interface codes such as device APIs, device driver, and device controller from the specification so that verified hardware and software codes can be synthesized without extra efforts.

• Journal of the Korean Society of Systems Engineering
• /
• v.9 no.1
• /
• pp.47-53
• /
• 2013

The object of this study is to define systematically for outputs of Verification Process among the system life cycle process based on ISO/IEC 15288 for power supply system, which is one of the importance sub-systems to configure the LRT system. Furthermore, to prevent various problem in advance that can occur in the Transition LRT's power supply to be completed Integration. For this purpose, traceability of verification requirement and outputs. should be managed to use verification for system requirement and data processing tool. by system engineering techniques of system life cycle process based on ISO/IEC 15288 to LRT system.