• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.21-21
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• 2010

• 플랜트 저널
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• 제14권1호
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• pp.47-51
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• 2018

본 연구에서는 석탄화력발전의 출력 감소가 계통한계가격과 온실가스감축량에 어떻게 영향을 미치는지 분석하였다. 분석방법은 국영 발전회사에서 이용하는 전력거래예측프로그램을 이용하였으며 전력계통의 운영조건은 제7차 전력수급기본계획의 전력수요와 전원구성을 근거로 하였다. 분석결과 전체 석탄화력발전의 최대출력을 29 [%]까지 감소한 경우 계통한계가격은 감소전과 비교하여 12 [%p] 상승하고 온실가스 배출량은 9,966 [kton] 감축되었다. 또한 석탄화력발전기 전체 용량의 30 [%]에 해당하는 저효율 석탄화력발전기 16기를 정지한 경우 계통한계가격은 14 [%p] 까지 증가하였고 온실가스 배출량은 12,574[kton]까지 감축 가능함을 알 수 있었다.

• 한국대기환경학회:학술대회논문집
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• 한국대기환경학회 2008년도 추계학술대회 논문집
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• pp.228-229
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• 2008

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2007년도 춘계학술대회 논문집
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• pp.67-70
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• 2007

LTCC (Low Temperature Co-fired Ceramic) has been emerged as a promising technology in packaging industry. In this technology the lamination and the sintering process are very important because they change the permittivity of ceramics and the dimension of metal pattern which have influences on electric property. In this paper we studied on influence of the permittivity and the dimension change by lamination pressure and sintering temperature of LTCC process. As a results, permittivity increase along with increasing of lamination pressure and sintering temperature.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2003년도 추계학술대회논문집
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• pp.101-106
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• 2003

Recent electronic equipment becomes smaller, more functional, and more complex. According to these trends, LTCC(low temperature co-fired ceramic) has been emerged as a promising technology in packaging industry. It consists of multi-layer ceramic sheet, and the circuit has 3D structure. In this technology via hole formation plays an important role because it provides an electric path for the packaging interconnection network. Therefore via hole quality is very important for ensuring performance of LTCC product. Via holes are formed on the green sheet that consists of ceramic(before sintering) layer and PET(polyethylene Terephthalate) one. In this paper we found the correlation between hole quality and process condition such as ceramic thickness, and tool size. The shear behavior of double layer sheet by micro hole punching which is different from that of single layer one was also discussed.

• 전기학회논문지
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• 제56권7호
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• pp.1288-1293
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• 2007

In this paper, a compact triplexer has been implemented for Cellular/GPS/USPCS applications. In order to realize the proposed triplexer, we use a low-temperature co-fired ceramic (LTCC) substrate to enable a fully compact integrated module using a multi-layer high-density architecture, and conjugate-match the channels instead of the open matching technique. The three dimensional design capability of LTCC substrates can reduce the overall size of the triplexer, resulting in dimensions on the order of $3.2\;mm\;{\times}\;2.5\;mm\;{\times}\;1\;mm$. The measured result shows that the triplexer has, in Cellular/GPS/USPCS bands, the insertion loss of less than 0.5dB, less than 1.7dB, and less than 0.9dB in order. Also, the triplexer has an isolation of more than 15dB in the cellular and USPCS bands and an isolation of more than 20dB in the GPS band.

• 소성∙가공
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• 제16권5호통권95호
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• pp.396-400
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• 2007

LTCC(Low Temperature Co-fired Ceramic) which offers a good performance to produce multilayer structures with electronic circuits and components has emerged as an attractive technology in the electronic packaging industry. In LTCC module fabrication process, the lamination and the sintering are very important processes and affect the electrical characteristics of the final products because the processes change the permittivity of ceramics and the dimension of the circuit patterns which have influences on electronic properties. This paper discusses the influence of lamination pressure and sintering temperature on the permittivity and the dimensional change of LTCC products. In the present investigation, it is shown that the permittivity increases along with increasing of the lamination pressure and the sintering temperature.

• 소성∙가공
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• 제14권3호
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• pp.277-281
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• 2005

LTCC(Low temperature co-fired ceramic) is being recognized as a significant packaging material of electrical devices for the advantages such as relatively low temperature being needed for process, low conductor resistance and high printing resolution. In the process of LTCC electrical devices, the punched via-hole quality is one of the most important factors on the performance of the device. However, its mechanism is very complicated and optimization of the process seems difficult. In this paper, to clarify the process, via-hole punching experiments were carried out and the punched holes were examined in terms of their burr formation. The effects of thickness of PET sheet, ceramic sheet and punch-to- die clearance on via-hole quality were also discussed. Optimum process conditions are proposed and a factor $\kappa$ is introduced to express effect of the process variables.

• 소성∙가공
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• 제13권1호
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• pp.65-71
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• 2004

Recent electronic equipment becomes smaller, more functional, and more complex. According to these trends, LTCC(low temperature co-fired ceramic) has been emerged as a promising technology in packaging industry. It consists of multi-layer ceramic sheet, and the circuit has 3D structure. In this technology via hole formation plays an important role because it provides an electric path for the packaging interconnection network. Therefore via hole qualify is very important for ensuring performance of LTCC product. Via holes are formed on the green sheet that consists of ceramic(before sintering) layer and PET(polyethylene terephthalate) one. In this paper we found the correlation between hole quality and process condition such as PET thickness and ceramic thickness. The shear behavior of double layer sheet by micro hole punching which is different from that of single layer one was also discussed.

• ETRI Journal
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• 제28권3호
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• pp.347-354
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• 2006

The characteristic variation of 3-dimensional (3-D) solenoid-type embedded inductors is investigated. Four different structures of a 3-D inductor are fabricated by using a low-temperature co-fired ceramic (LTCC) process, and their s-parameters are measured between 50 MHz and 5 GHz. The circuit model parameters of each building block are optimized and extracted using the partial element equivalent circuit method and an HSPICE circuit simulator. Based on the model parameters, the characteristics of the test structures such as self-resonant frequency, inductance, and quality (Q) factor are analyzed, and predictive modeling is applied to the structures composed of a combination of the modeled building blocks. In addition, characteristic variations of the 3-D inductors with different structures using extracted building blocks are also investigated. This approach can provide a characteristic estimation of 3-D solenoid embedded inductors for structural variations.