• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.34-41
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• 2001

Semiconductors performing digital clocking are a main source of radiated emission noise. Therefore, the most secure method of reducing emission noise is to reduce emission radiated from semiconductors; an application of an absorber to the surface of semiconductors is one of these methods, too. However, in reality, it is difficult to achieve as much effect of noise reduction as expected by using only absorber. It is confirmed by experiment in this paper that a loop area within chip has no correlation with radiated emission noise and it is clarified why the existing absorber fails to achieve a satisfactory effect of emission noise reduction. Besides, a new type of chip coating absorber has been developed which can cover up to semiconductor out lead by using ferrite coating material of ferrite/epoxy acrylate substance using only permeability loss out of electromagnetic wave reduction characteristics of materials. As a result of evaluating radiated emission noise by applying this coating absorber to semiconductor device, it could be confirmed that emission noise decreased from about 3 ㏈ up to 20㏈ depending on frequency.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.4
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• pp.419-428
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• 1986

While three most important aspects of line codes are the de-free, the minimum-bandwidth, and the self-clocking properties, the only TIBr, VMDBr, RMD3r, RMD4r codes possess all of these properties. This paper is to report the results of an experimental performance study of VMDB5. The encoder and decoder of VMDB5 and the pulse shaper have been inplemented. Power spectra, eye patterns, and error probabilities are experimentally measured, confirming the theoreticla performance predictions. It has been observed that the NRZ pulse shaping reliable transmission is possible with no extra equalization even in teh case when the -3dB channel bandwith is only half the Nyquist bandwidth.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.486-495
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• 2006

In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.

• Progress in Superconductivity
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• v.6 no.1
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• pp.7-12
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• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• Progress in Superconductivity and Cryogenics
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• v.7 no.1
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• pp.9-12
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• 2005

We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• Proceedings of the Korean Association of Geographic Inforamtion Studies Conference
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• 2010.06a
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• pp.53-60
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• 2010

위치 기반 서비스(Location-Based Services: LBS)에서 질의 요청자가 자신의 위치 정보와 원하는 질의를 전송하면, 위치 기반 서버는 이를 기반으로 질의를 처리하고 결과를 전송한다. 이 때 질의 요청자는 자신의 정확한 위치 좌표를 서버에 전송하기 때문에 개인 정보가 악용될 수 있는 위험에 노출된다. 이러한 문제를 해결하기 위하여 제안된 연구는 크게 Location Clocking 기법과 Private Information Retrieval(PIR) 기법으로 분류된다. Location Cloaking 기법은 사용자의 위치 좌표를 k-1개의 다른 사용자와 함께 묶어 하나의 Cloaking 영역을 생성하고 이를 바탕으로 질의를 처리한다. 그러나 영역에 대한 질의 후보 집합을 결과로 전송하므로 사용자에게 노출되는 POI 수가 증가하는 문제점을 지닌다. PIR은 암호화 기법으로 위치 기반 서버나 공격자에게 사용자의 위치와 질의 타입을 드러내지 않고 질의를 수행한다. 그러나 암호화 된 질의 결과로 사용자에게 데이터 전체를 전송하기 때문에 막대한 통신비용을 초래한다. 따라서 본 논문에서는 Location Cloakng과 PIR 기법의 장점을 결합하여 사용자의 개인 정보와 위치 기반 서버의 POI 정보 보호를 고려한 Approximate k-최근접점 질의 처리 알고리즘을 제안한다. 질의 전송시, 질의 요청자는 Cloaking 영역을 생성하여 위치 좌표를 감추고, 질의 결과 전송 시 Cloaking 영역에 제한된 PIR 프로토콜을 적용한다. 또한 k-최근접점 질의 수행시, 반환되는 POI의 수를 최소화하고, 정확도 높은 질의 결과를 만족하기 위해 Overlapping parameter를 적용한 색인 기법을 제안한다.

• Archives of Plastic Surgery
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• v.47 no.6
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• pp.495-504
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• 2020

The primary procedural components of deviated nose correction are as follows: osteotomy to correct bony deviation, septal deviation correction, manipulation of the dorsal septum to correct upper lateral cartilage deviation, and correction of functional problems (manipulation for correction of internal valve collapse and hypertrophy of the inferior turbinate). The correction of tip and nostril asymmetry cannot be overemphasized, because if tip and nostril asymmetry is not corrected, patients are unlikely to provide favorable evaluations from an aesthetic standpoint. Tip asymmetry, deviated columella, and resulting nostril asymmetry are primarily caused by lower lateral cartilage problems, which include deviation of the medial crura, discrepancy in the height of the medial crura, and asymmetry or deformity of the lateral crura. However, caudal and dorsal septal deviation, which is a more important etiology, should also be corrected. A columellar strut graft, correction of any discrepancy in the height of the medial crura, or lateral crural correction is needed to correct lower lateral cartilage deformation depending on the type. In order to correct caudal septal deviation, caudal septal shortening, repositioning, or the cut-and-suture technique are used. Surgery to correct dorsal septal deviation is performed by combining a scoring and splinting graft, a spreader graft, and/or the clocking suture technique. Moreover, when correcting a deviated nose, correction of asymmetry of the alar rim and alar base should not be overlooked to achieve tip and nostril symmetry.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1055-1061
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• 2002

Conventional TSPC D flip-flop has the advantages of high speed, simple clock distribution, and no racing because of the single phase clocking strategy and its simple structure. But, it suffers from glitch, clock slope sensitivity and unbalanced propagation delay problems. Therefore, a new dynamic D flip-flop, which improves these disadvantages, is proposed. The main idea of this paper is DS(Discharge Suppression) scheme, which suppresses unnecessary discharge. As a result, the proposed structure is free from glitch problem and it improves maximum clock slope immunity from 0.25ns to Ins. Also, it uses only 8 transistors and it Is demonstrated that high speed operation is feasible by balancing propagation delay time.

• Progress in Superconductivity
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• v.7 no.2
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.