• ETRI Journal
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• v.30 no.2
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• pp.275-281
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• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.57-63
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• 2009

In this Paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuit is composed of CDR(Clock and Data Recovery) block and PLL(Phase Locked Loop) block. Lock dynamics is accomplished on the first data transition and data are sampled in the optimal point. The CDR circuit is realized in 0.35um CMOS process technology. With input pseudo-random bit sequences(PRBS) of $2^7-1$, the simulations show 17ps peak-to-peak retimed data jitter characteristics. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.193-199
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• 2008

A combined clock and data recovery (CDR) circuit with adaptive cancellation of data-dependent jitter (DDJ) is constructed in all-digital architecture which is amenable to deep submicron technology. The DDJ canceller uses an adaptive FIR filter to compen-sate for any unknown channel characteristic. The proposed CDR decreases jitter in the recovered clock since the DDJ canceller significantly cancels out incoming jitter caused by inter-symbol interference.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.188-193
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• 2003

This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.2
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• pp.324-328
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• 2012

A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.287-292
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• 2016

A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from $2^{31}-1$ PRBS input data has 0.011-UI rms jitter.

• Journal of Sensor Science and Technology
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• v.12 no.4
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• pp.191-197
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• 2003

Due to explosive increase of internet usage, broadband data transmission using optical fibers is broadly used. In order to decrease distortion during long distance transmission, the optical signal need to be restored, typically, by converting the optical signal into the electrical signal. The optical signal is converted into the electrical signal using a photo-diode, and then a clock-and-recovery (CDR) circuit is used to recover the clock and retime the data. In this study, a clock-and-data recovery circuit has been designed using a standard 1.8 V $0.18\;{\mu}m$ CMOS process. With this CDR circuit, the improved phase detector and charge pump have been utilized. Also, by using a ring oscillator, the CDR circuit can recover clock and data from broadband multi-rate data ranging between 750 Mb/s and 2.85 Gb/s.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.899-905
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• 2017

This paper presents a reference-less dual loop clock and data recovery (CDR) circuit that supports a data rate of 2.496 Gb/s for the mobile industry processor interface (MIPI) M-PHY. An adaptive loop bandwidth scheme is used to implement the fast lock time maintaining a low time jitter. To this scheme, the proposed CDR consists of two loops for a frequency locked loop and a phase locked loop. The proposed 2.496 Gb/s reference-less dual loop CDR is designed using a 65 nm CMOS process with 1.2 V supply voltage. The simulated peak-to-peak jitter of output clock is 9.26 ps for the input data of 2.496 Gb/s pseudo-random binary sequence (PRBS) 15. The active area and power consumption of the implemented CDR are $470{\times}400{\mu}m^2$ and 6.49 mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.82-86
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• 2009

This work is design of clock and data recovery circuit using system clock. This circuit is composed by PLL(Phase Locked Loop) to make system clock and data recovery circuit. The data recovery circuit using 1/4-rate phase picking Detector helps to reduce clock frequency. It is advantageous for high speed PLL. It can achieve a low jitter operation. The designed CDR(Clock and data recovery) has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and an active area $1{\times}1mm^2$.